search for: isshufflemasklegal

Displaying 4 results from an estimated 4 matches for "isshufflemasklegal".

2011 Mar 27
2
[LLVMdev] Long-Term ISel Design
...(vector_shuffle node:$lhs, node:$rhs), [{ return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N)); }], SHUFFLE_get_shuf_imm>; Ok, so far this is exactly the same as today. What we eliminate is this: void X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { ... isShuffleMaskLegal(...) } bool X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const { // FIXME: pshufb, blends, shifts. return (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||...
2011 Mar 18
0
[LLVMdev] Long-Term ISel Design
On Mar 17, 2011, at 9:32 AM, David A. Greene wrote: > Chris Lattner <clattner at apple.com> writes: >>> 1. We have special target-specific operators for certain shuffles in X86, >>> such as X86unpckl. > >> It also eliminates a lot of fragility. Before doing this, X86 >> legalize would have to be very careful to specifically form shuffles >> that
2011 Mar 17
2
[LLVMdev] Long-Term ISel Design
Chris Lattner <clattner at apple.com> writes: >> 1. We have special target-specific operators for certain shuffles in X86, >> such as X86unpckl. > It also eliminates a lot of fragility. Before doing this, X86 > legalize would have to be very careful to specifically form shuffles > that it knew isel would turn into (e.g.) unpck operations. Now > instead of
2011 Apr 09
0
[LLVMdev] Long-Term ISel Design
...shuffles. Since tblgen doesn't >> generate table based matching for *any* shuffles, all of the matching >> code would end up as C++ code in X86ISelDagToDag, which would give us >> all of the problems we had before by moving to X86ISD nodes. > > bool X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, > EVT VT) const { > // FIXME: pshufb, blends, shifts. > return (VT.getVectorNumElements() == 2 || > ShuffleVectorSDNode::isSplatMask(&M[0], VT) || > isMOVLMask(M, VT) || >...