search for: isreturn

Displaying 20 results from an estimated 52 matches for "isreturn".

2013 Mar 21
0
[LLVMdev] Hit a snag while attempting to write a backend - any advice?
Hi Lee, > let isReturn = 1, isTerminator = 1, isBarrier = 1 in > { > def RET : BitscuitInst<(outs),(ins),"JMP\tR6",[(Bitscuit_return)]>; > > def JMP : BitscuitInst<(outs), (ins jmptarget:$dst),"JMP\t$dst",[(br > bb:$dst)]>; > } Ah! It looks like the isReturn is to blame...
2018 Apr 09
2
Issue with shrink wrapping
...the stack pointer is overwritten with an incorrect value. I've "fixed" this by modifying `ShrinkWrap::useOrDefCSROrFI` to explicitly check for the stack pointer register (using `TLI.getStackPointerRegisterToSaveRestore`) and also to ignore tall call instructions (`isCall() && isReturn()`), since they implictly use SP (for AArch{32,64} at least). Does this look correct? Are there alternatives? Shouldn't `ShrinkWrap::useOrDefCSROrFI` also check whether or not `MachineInstr::Frame{Setup,Destroy}` flags are set? In that case, I suppose an alternative slution would be to ensur...
2018 Apr 10
0
Issue with shrink wrapping
...quot; this by modifying `ShrinkWrap::useOrDefCSROrFI` to explicitly check > for the stack pointer register (using > `TLI.getStackPointerRegisterToSaveRestore`) This part sounds ok to me. Can you put up a patch please? > and also to ignore tall call > instructions (`isCall() && isReturn()`), since they implictly use SP (for > AArch{32,64} at least). Calls are handled through the regmask check, and return blocks should be handled by the common-dominator call. Did you run into any issues with this? Marking blocks containing `isReturn` instructions as used will basically make shr...
2017 Nov 29
3
PPC64 Disassembler
...erLLVMC.cpp:87 - "const bool can_branch = mc_disasm_ptr->CanBranch(inst);"), while trying to set the next breakpoint. On this case, the instruction is the "bne cr7,0x2000092c", which is a branch, but at llvm/lib/MC/MCInstrDesc.cpp:35 - "if (isBranch() || isCall() || isReturn() || isIndirectBranch())" it returns false, making lldb do not set the correct breakpoint, so the execution does not stop at next line, which should be the "step over" behavior. The variable "Flags" for the disassembled instruction does not have the branch flag. I have tr...
2008 Oct 30
2
[LLVMdev] Target description flags for instructions which may trap
...causing a miscompilation by hoisting a divide by zero instruction out of the loop. Clearly this pass needs to be made aware that this is not safe. The current test in the MachineLICM is as follows: // Ignore stuff that we obviously can't hoist. if (TID.mayStore() || TID.isCall() || TID.isReturn() || TID.isBranch() || TID.hasUnmodeledSideEffects()) return false; Setting hasSideEffects = 1 seems to work, but I'm not sure if that's the intended use of this flag. I notice that divide / remainder instructions for other architectures are not marked in this way. Also it is a...
2013 Mar 18
5
[LLVMdev] Hit a snag while attempting to write a backend - any advice?
Hi, I've been experimenting with writing a backend for LLVM (3.2) (having already written a frontend http://savourysnax.github.com/EDL), everything was going reasonably ok ( calls/returns, epilogue, prologue, etc are all working), up until I tried to place support for conditional branches. Given this simple program : int test(int c,int d) { if (c) { return
2007 Jan 11
1
[LLVMdev] Pattern matching questions
...t;? Or even something >>> like >>> !strconcat("bi ", !strconcat("$", "lr")). >> >> >> Yep, $$ should work. > > It doesn't. Here's the pattern: > > let isTerminator = 1, isBarrier = 1, noResults = 1 in { > let isReturn = 1 in { > def RET: BRForm<0b00010101100, (ops), > "bi $$lr", > BranchResolv, > [(retflag)]>; > } > } > > Output from make: > > llvm[0]: Building SPU.td code emitter with tblg...
2016 Mar 22
1
New intrinsic property IntrOnlyWrite
...return true /// for instructions whose effects are captured by: /// /// 1. Their operand list and implicit definition/use list. Register use/def /// info is explicit for instructions. /// 2. Memory accesses. Use mayLoad/mayStore. /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. Now you initially reported that "TableGen will (correctly) complain about a mismatch of mayLoad and hasSideEffects", I believe this is incorrect considering the above description. -- Mehdi > > At the IR level, the definition of "mayHaveSideEffects" is more...
2007 Sep 24
0
[LLVMdev] RFC: Tail call optimization X86
...if (RI->getReturnValue()==0 || + std::find(RI->op_begin(), RI->op_end(), + (Value*)&I) != RI->op_end()) + return true; + } + } + return false; +} Also, shouldn't this function be "static"? let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL", + []>; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*} $dst # TAI...
2007 Jan 10
0
[LLVMdev] Pattern matching questions
...t;bi \$lr" works? Or "bi $$lr"? Or even something >>like >>!strconcat("bi ", !strconcat("$", "lr")). > > > Yep, $$ should work. It doesn't. Here's the pattern: let isTerminator = 1, isBarrier = 1, noResults = 1 in { let isReturn = 1 in { def RET: BRForm<0b00010101100, (ops), "bi $$lr", BranchResolv, [(retflag)]>; } } Output from make: llvm[0]: Building SPU.td code emitter with tblgen tblgen: /work/scottm/llvm/utils/TableGen/Code...
2007 Sep 23
2
[LLVMdev] RFC: Tail call optimization X86
The patch is against revision 42247. -------------- next part -------------- A non-text attachment was scrubbed... Name: tailcall-src.patch Type: application/octet-stream Size: 62639 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070923/4770302f/attachment.obj>
2017 Nov 30
2
PPC64 Disassembler
...e > > > > trying to set the next breakpoint. > > > > > > > > On this case, the instruction is the “bne cr7,0x2000092c”, which is a > > branch, > > > > but at llvm/lib/MC/MCInstrDesc.cpp:35 – > > > > “if (isBranch() || isCall() || isReturn() || isIndirectBranch())” it > returns > > false, > > > > making lldb do not set the correct breakpoint, so the execution does not > > stop > > > > at next line, which should be the “step over” behavior. > > > > > > > > The variable “Fl...
2007 Jan 09
2
[LLVMdev] Pattern matching questions
On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5
2017 Sep 19
1
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...(ins IRF32:$target, variable_ops), [(my_call IRF32:$target)]> { let isCall = 1; let usesCustomInserter = 1; } def Custom_RETURN : Pseudo<(outs), (ins variable_ops), [(my_ret)]> { let isReturn = 1; let usesCustomInserter = 1; } but when I compile the following C code: int foo(int); int bar() { return foo(42); } it crashes with the following dump: fatal error: error in backend: Cannot select: 0x1ede6ae3648: ch,glue = callseq_end 0x1ede6ae35e0, TargetConstant:i32<0>, TargetGlobalAd...
2017 Nov 30
2
PPC64 Disassembler
...e > > > > trying to set the next breakpoint. > > > > > > > > On this case, the instruction is the “bne cr7,0x2000092c”, which is a > > branch, > > > > but at llvm/lib/MC/MCInstrDesc.cpp:35 – > > > > “if (isBranch() || isCall() || isReturn() || isIndirectBranch())” it > returns > > false, > > > > making lldb do not set the correct breakpoint, so the execution does not > > stop > > > > at next line, which should be the “step over” behavior. > > > > > > > > The variable “Fl...
2012 Aug 07
0
[LLVMdev] [RFC] Hexagon insn table refactoring
...t <(outs), (ins PredRegs:$Pu, IntRegs:$Rs), "if (!$Pu.new) jumpr:t $Rs", P, C> { bits<2> Pu; bits<5> Rs; IClass = 0b0101; Inst{27-21} = 0b0011011; Inst{12-11} = 0b11; Inst{9-8} = Pu; Inst{20-16} = Rs; }; let isReturn = 1, isBarrier = 1, isTerminator = 1 in def JMPR_cdnNotPt_V3 : V3_J2_jumprfnewpt<>, Requires<[HasV3T]>; The insn class would be in a separate file included in the file where the insns are defined. So its refactoring will mean that the way in which insns are d...
2007 Aug 08
1
[LLVMdev] Destination register needs to be valid after callee saved register restore when tail calling
...ome X86InstrInfo.td foo magic maybe ?) Or do i have to insert code into PEI::saveCalleeSavedRegisters to detect that there is a tail called function that uses a callee saved register and move it to another (EAX). that's how the TAILJMP instruction looks: let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL jmpr", []>; btw. i am currently working with llvm-2.0 codebase. thanks for any help regards arnold
2013 Jan 27
1
[LLVMdev] Clarification about callee saved regs and MachineRegisterInfo::isPhyRegUsed
Hi, I am confused about the call to isPhyRegUsed in calculateCalleeSavedRegisters: if (Fn.getRegInfo().isPhysRegUsed(Reg)) { // If the reg is modified, save it! CSI.push_back(CalleeSavedInfo(Reg)); } It seems that isPhyRegUsed returns true if the register is read or written in the function. If this is right, why do we save a register if it is only read in the function ?? I would have
2007 Aug 08
0
[LLVMdev] Destination register needs to be valid after callee saved register restore when tail calling
...to express the question whether there is a way to persuade the code generator to use another register to load (or move) the function pointer to (right before the callee saved register restore) but thinking a little further that's nonsense. something like let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1, ifDestRegisterisCalleeSavedEmitAMoveToECXAndJumpToThat=1 in def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL jmpr", []>; On 8 Aug 2007, at 18:27, Dale Johannesen wrote: > Inserting a pseudo b...
2015 Nov 19
2
Way to print all the properties of a given def
Does anybody know is there is a way to print all the property values for a given def? For example I have a following instruction definition in the .td file let isReturn = 1, isTerminator = 1, hasDelaySlot=1, isBarrier = 1, isCodeGenOnly = 1, Inst = 0x44004800 in { def RET : InstBR<0x1, (outs), (ins), "l.jr\tr9", [(retflag)]>; } Ultimately when I track it down the def tracks down to class Instruction in inclu...