search for: isrenameable

...nts) and thus should not be changed. I'd like to propose adding a bit to MachineOperand (by overloading the meaning of the IsKill bit for defs, so no extra storage would be required), that tracks whether a given register definition was a virtual register before RA. I'll throw out 'IsRenameable' for a potential name. Register definitions created with virtual registers would have this bit set. This bit should be verifiable until after RA. Register definitions created after RA (presumably with physical registers) would not have this bit set. I believe the only potential for this...

...ould not be changed. I'd like to propose adding a > bit to MachineOperand (by overloading the meaning of the IsKill bit for > defs, so no extra storage would be required), that tracks whether a given > register definition was a virtual register before RA. I'll throw out > 'IsRenameable' for a potential name. > > > > Register definitions created with virtual registers would have this bit > set. This bit should be verifiable until after RA. Register definitions > created after RA (presumably with physical registers) would not have this > bit set. I belie...

Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a

Hi Venu, This is happening because there is an implicit def of ECX on the COPY instruction. This was an issue on Hexagon as well. Let me give you some background. There are two kinds of implicit defs (and implicit uses, but I'll refer only to defs for brevity): (1) Those that indicate that some physical register (that is not an operand) is modified by a given instruction (EFLAGS is a good

Hi Venu, FWIW, I have a pass that does copy propagation after RA [1] (currently only within a basic block) that should be enabled some time in the not-too-distant future. It has been reviewed and accepted, but I'm currently working on getting a slight change to the MachineOperand representation [2] that should make the copy propagation change much simpler. I believe this change to

Hi Krzysztof, In one of your earlier emails in this thread you mentioned that you had some changes which add extra aliases for subregisters. Did you mean for X86? And is it extra register units that you added or aliases? I tried adding extra register units for X86 through some changes in CodeGenRegisters.cpp in TableGen but I am seeing a runtime error in one of my test cases possibly due to the

Hi, I've some problems/questions while implementing the BUILD_VECTOR primitive for a SIMD microcontroller... This microcontroller has two FPU units: UnitA and UnitB. UnitA has a bank of 512 registers named RegisterA_0 .. RegisterA_511. UnitB has a bank of 512 registers named RegisterB_0 .. RegisterB_511. The FPU instruction format has a 2 bits operand indicating which units are involved:

Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but