search for: isrenam

...nts) and thus should not be changed. I'd like to propose adding a bit to MachineOperand (by overloading the meaning of the IsKill bit for defs, so no extra storage would be required), that tracks whether a given register definition was a virtual register before RA. I'll throw out 'IsRenameable' for a potential name. Register definitions created with virtual registers would have this bit set. This bit should be verifiable until after RA. Register definitions created after RA (presumably with physical registers) would not have this bit set. I believe the only potential for...

...ould not be changed. I'd like to propose adding a > bit to MachineOperand (by overloading the meaning of the IsKill bit for > defs, so no extra storage would be required), that tracks whether a given > register definition was a virtual register before RA. I'll throw out > 'IsRenameable' for a potential name. > > > > Register definitions created with virtual registers would have this bit > set. This bit should be verifiable until after RA. Register definitions > created after RA (presumably with physical registers) would not have this > bit set. I...

Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature wh...

...> allocation > To: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > > > RDF has its own tests to detect the ability to rename any given > register. RefNodes that have "Fixed" flag are those where the register > cannot be changed. Having the isRenamable flag in MachineOperand would > help remove these tests. > > -Krzysztof > > > > > On 10/31/2017 11:24 PM, Raghavan, Venugopal via llvm-dev wrote: > > Hi Geoff/Krzyssztof, > > Wouldn't the isRenamable() change be required even for the RDF ba...

...ess the renaming is done right after RA when virtual registers are still present, which is what my current patch does, and is the source of complexity that I'm trying to eliminate). [1] https://reviews.llvm.org/D30751 [2] https://reviews.llvm.org/D39400 D39400 WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand. On 10/31/2017 5:49 AM, Raghavan, Venugopal via llvm-dev wrote: > Hi Krzysztof, > > Thanks a lot for taking the time to write a detailed explanation. I > think I understand things better now. > > I am trying to see if I can use RDF for X86 assuming I can...

...at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >>> >>> >>> RDF has its own tests to detect the ability to rename any given >>> register. RefNodes that have "Fixed" flag are those where the register >>> cannot be changed. Having the isRenamable flag in MachineOperand would help >>> remove these tests. >>> >>> -Krzysztof >>> >>> >>> >>> >>> On 10/31/2017 11:24 PM, Raghavan, Venugopal via llvm-dev wrote: >>> >>> Hi Geoff/Krzyssztof, >>&gt...

Hi, I've some problems/questions while implementing the BUILD_VECTOR primitive for a SIMD microcontroller... This microcontroller has two FPU units: UnitA and UnitB. UnitA has a bank of 512 registers named RegisterA_0 .. RegisterA_511. UnitB has a bank of 512 registers named RegisterB_0 .. RegisterB_511. The FPU instruction format has a 2 bits operand indicating which units are involved:

Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but