Displaying 14 results from an estimated 14 matches for "isregloc".
2013 Jan 27
2
[LLVMdev] lldb cannot display structure type for llvm3.2
I find the lldb cannot display structure type information, such as "print ArgLocs.size()" as follows,
-> 593 CCValAssign &VA = ArgLocs[i];
594 EVT ValVT = VA.getValVT();
595 ISD::ArgFlagsTy Flags = Ins[i].Flags;
596 bool IsRegLoc = VA.isRegLoc();
(lldb) print ArgLocs.size()
error: call to a function 'llvm::SmallVectorTemplateCommon<llvm::CCValAssign>::size() const' that is not present in the target
error: Couldn't materialize struct: Structure hasn't been laid out yet
I use Xcode 4.5.2 and my lldb ca...
2013 Jan 28
0
[LLVMdev] lldb cannot display structure type for llvm3.2
...t; I find the lldb cannot display structure type information, such as "print
> ArgLocs.size()" as follows,
>
> -> 593 CCValAssign &VA = ArgLocs[i];
> 594 EVT ValVT = VA.getValVT();
> 595 ISD::ArgFlagsTy Flags = Ins[i].Flags;
> 596 bool IsRegLoc = VA.isRegLoc();
> (lldb) print ArgLocs.size()
> error: call to a function
> 'llvm::SmallVectorTemplateCommon<llvm::CCValAssign>::size() const' that is
> not present in the target
> error: Couldn't materialize struct: Structure hasn't been laid out yet
>
>...
2012 Oct 26
1
[LLVMdev] Properly handling mem-loc arguments when prologue adjusts FP.
...guesses these
things automatically from the instructions, it wouldn't be able to guess
that. But here I'm just conjecturing - may not be relevant!
Thanks,
Stephen
[1]: LowerCall
...
// Arguments that can be passed in a register must be kept in the
// RegsToPass vector.
if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} else {
// Sanity check.
assert(VA.isMemLoc());
// Get the stack pointer if needed.
if (StackPtr.getNode() == 0) {
StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, getPointerTy());
}...
2016 Feb 01
2
TableGen customized node with mayStore attribute is deleted if there is no use
...[(set i32:$dst, (MoveFlag i32:$src))]>;
For example, I add this node into SDAG when I want to move the formal
argument from the specific register class to other register class. I
implement it in LowerFormalArguments() like this:
....
for (auto &VA : ArgLocs) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
VReg = RegInfo.createVirtualRegister(&FOO::BRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
SDValue ArgIn_copy = DAG.getNode(F...
2012 Aug 16
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...scribing the calling conventions in tablegen so that first registers
are used and to fall back to the stack if these do not suffice.
However, this is not enough and lowering calls and returns have to
reflect this, too. Currently, most targets also do not support this
(there is assertion: assert(VA.isRegLoc() && "Can only return in
registers!")).
How important is this feature? Is it save to ignore it? Is there some
guide how to implement such a hybrid passing of return values (partly
in registers, partly on the stack)? Currently, the TriCore back-end is
not able to compile functions...
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
...s dangerous. It's probably better to check
whether the last call is a tail call on the fly as you are processing
the return node.
8.
-
- SDOperand Chain = Op.getOperand(0);
- SDOperand Flag;
-
- // Copy the result values into the output registers.
- if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
- RVLocs[0].getLocReg() != X86::ST0) {
- for (unsigned i = 0; i != RVLocs.size(); ++i) {
- CCValAssign &VA = RVLocs[i];
- assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand
(i*2...
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
first off thanks to you and Chris for taking time.
On 6 Sep 2007, at 00:57, Evan Cheng wrote:
> We'd like to see tail call optimization to be similar to the target
> independent lowering of ISD::CALL nodes. These are auto-generated
> from ???CallingConv.td files. Some target specific details such as
> function address register (ECX in your example) should be coded in
2012 Aug 16
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...conventions in tablegen so that first registers
> are used and to fall back to the stack if these do not suffice.
> However, this is not enough and lowering calls and returns have to
> reflect this, too. Currently, most targets also do not support this
> (there is assertion: assert(VA.isRegLoc() && "Can only return in
> registers!")).
>
> How important is this feature? Is it save to ignore it? Is there some
> guide how to implement such a hybrid passing of return values (partly
> in registers, partly on the stack)? Currently, the TriCore back-end is
>...
2012 Aug 17
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...tablegen so that first registers
>> are used and to fall back to the stack if these do not suffice.
>> However, this is not enough and lowering calls and returns have to
>> reflect this, too. Currently, most targets also do not support this
>> (there is assertion: assert(VA.isRegLoc() && "Can only return in
>> registers!")).
>>
>> How important is this feature? Is it save to ignore it? Is there some
>> guide how to implement such a hybrid passing of return values (partly
>> in registers, partly on the stack)? Currently, the TriCo...
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
...hether the last call is a tail call on the fly as you are processing
> the return node.
Will do so.
> 8.
> -
> - SDOperand Chain = Op.getOperand(0);
> - SDOperand Flag;
> -
> - // Copy the result values into the output registers.
> - if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
> - RVLocs[0].getLocReg() != X86::ST0) {
> - for (unsigned i = 0; i != RVLocs.size(); ++i) {
> - CCValAssign &VA = RVLocs[i];
> - assert(VA.isRegLoc() && "Can only return in registers!");
> - Chain = DAG.getCopyToReg(Chain, VA.getLocR...
2013 Feb 02
0
[LLVMdev] Moving return value registers from MRI to return instructions
...Value Chain,
RVLocs, *DAG.getContext());
CCInfo.AnalyzeReturn(Outs, RetCC_X86);
- // Add the regs to the liveout set for the function.
- MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
- for (unsigned i = 0; i != RVLocs.size(); ++i)
- if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
- MRI.addLiveOut(RVLocs[i].getLocReg());
-
SDValue Flag;
-
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
@@ -1666,6 +1659,7 @@ X86TargetLowering::...
2012 Aug 17
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...first registers
>>> are used and to fall back to the stack if these do not suffice.
>>> However, this is not enough and lowering calls and returns have to
>>> reflect this, too. Currently, most targets also do not support this
>>> (there is assertion: assert(VA.isRegLoc() && "Can only return in
>>> registers!")).
>>>
>>> How important is this feature? Is it save to ignore it? Is there some
>>> guide how to implement such a hybrid passing of return values (partly
>>> in registers, partly on the stack)?...
2015 Nov 25
2
need help for customized backend LowerFormalArguments
.../ Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_FOO);
for (auto &VA : ArgLocs) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
const unsigned VReg =
RegInfo.createVirtualRegister(&FOO::PRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
InVals.push_back(A...
2018 Sep 14
6
Function calls keep increasing the stack usage
Hi everyone,
I found that LLVM generates redundant code when calling functions with
constant parameters, with optimizations disabled.
Consider the following C code snippet:
int foo(int x, int y);
void bar()
{
foo(1, 2);
foo(3, 4);
}
Clang/LLVM 6.0 generates the following assembly code:
_bar:
subl $32, %esp
movl $1, %eax
movl $2, %ecx
movl $1, (%esp)
movl $2, 4(%esp)
movl %eax, 28(%esp)
movl