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I have a fairly complicated setup. Extensions (1,2 and 3). In 3 - I execute AGI in java which plays few wav files depending on external parameters. Can I have a dial plan inside my AGI? If not, how do I accomodate user who needs to reach extension 2 from my agi? I have tried stream file and get data but the two commands did not work at all.

...p;fn) { // perform a final pass over the instructions and compute spill // weights, coalesce virtual registers and remove identity moves ... for (unsigned i = 0; i < mii->getNumOperands(); ++i) { const MachineOperand& mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt =...

On 08/09/05, Chris Lattner <sabre at nondot.org> wrote: > This code isn't actually replacing the virtual register with a physreg. Then why changing its optype? It makes the assertion fails: MachineOperand& MO = inst.getOperand(n); if (MRegisterInfo::isVirtualRegister(MO.getReg())) { assert(MachineOperand::MO_VirtualRegister == MO.getType()); ... } Is that alright? Some

...amp;& "Immediate size not set!"); > - return 0; > - } > -} > - > -/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended > register? > -/// e.g. r8, xmm8, etc. > -bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) { > - if (!MO.isRegister()) return false; > - switch (MO.getReg()) { > - default: break; > - case X86::R8: case X86::R9: case X86::R10: case X86::R11: > - case X86::R12: case X86::R13: case X86::R14: case X86::R15: > - case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: &g...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...} this->vrm->grow(); this->reg_mapping->grow(); this->vrm->assignVirt2StackSlot(new_reg, slot); for(unsigned t = 0; t < mi->getNumOperands(); t++) { MachineOperand & mo_aux = mi->getOperand(t); if(mo_aux.isRegister() && mo_aux.getReg() && mo_aux.isUse()) { if(mo_aux.getReg() == v_reg) { mo_aux.setReg(new_reg); this->reg_mapping->set_color_spilled_register (new_reg, p_reg);...

Thx again Evan for the review. Here's a new patch for the JIT in itself. The major changes are: 1) A JITMemoryManager now has a flag saying "I require to know the size of what you want to emit" 2) DwarfJITEmitter is augmented with GetSize* functions 3) JITEmitter::startFunction checks if the JITMemoryManager requires to know the size. If so, it computes it and gives it through the

So what addIntervalsToSpills returns are new intervals to allocate with infinite weights, right? And I need not to allocate the old interval. Should hasStackSlot return true on its register then? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Well, someone correct me if am wrong, but, you still have to allocate > physical registers to them,

...s<LoopInfo>(); for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { [...] for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { const MachineOperand &mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->getOperand(i).setReg(reg); Doesn't that last statement actually do t...

.../// virtual is used twice or more in an instruction, it only needs one /// physical register. std::set<unsigned> seen_regs; for(unsigned u = 0; u < mi->getNumOperands(); u++) { const MachineOperand & mo = mi->getOperand(u); if(mo.isUse() && mo.isRegister() && mo.getReg()) { if(MRegisterInfo::isVirtualRegister(mo.getReg())) { unsigned v_reg = mo.getReg(); if(this->vrm->hasStackSlot(v_reg)) { int slot = this->vrm->getStackSlot(v_reg); // First, try to fold the memory reference...

...if (PointerSize == 8) { > + EmitInt64(LabelPtr - BaseLabelPtr); > + } else { > + EmitInt32(LabelPtr - BaseLabelPtr); > + } > + > + BaseLabelPtr = LabelPtr; > + IsLocal = true; > + } > + > + // If advancing cfa. > + if (Dst.isRegister() && Dst.getRegister() == > MachineLocation::VirtualFP) { > + if (!Src.isRegister()) { > + if (Src.getRegister() == MachineLocation::VirtualFP) { > + EmitInt8(dwarf::DW_CFA_def_cfa_offset); > + } else { > + EmitInt8(dwarf::DW_CFA_de...

...mitInt64(LabelPtr - BaseLabelPtr); >> + } else { >> + EmitInt32(LabelPtr - BaseLabelPtr); >> + } >> + >> + BaseLabelPtr = LabelPtr; >> + IsLocal = true; >> + } >> + >> + // If advancing cfa. >> + if (Dst.isRegister() && Dst.getRegister() == >> MachineLocation::VirtualFP) { >> + if (!Src.isRegister()) { >> + if (Src.getRegister() == MachineLocation::VirtualFP) { >> + EmitInt8(dwarf::DW_CFA_def_cfa_offset); >> + } else { >> + E...

Hi everyone, Here's a patch that enables exception handling when jitting. I've copy/pasted _many_code from lib/Codegen/DwarfWriter.cpp, so we may need to factorize it, but the functionality is there and I'm very happy with it :) lli should now be able to execute the output from llvm-gcc when using exceptions (the UnwindInst instruction is not involved in this patch). Just add the

...== 8) { > + MCE->emitInt64(LabelPtr - BaseLabelPtr); > + } else { > + MCE->emitInt32(LabelPtr - BaseLabelPtr); > + } > + > + BaseLabelPtr = LabelPtr; > + IsLocal = true; > + } > + > + // If advancing cfa. > + if (Dst.isRegister() && Dst.getRegister() == > MachineLocation::VirtualFP) { > + if (!Src.isRegister()) { > + if (Src.getRegister() == MachineLocation::VirtualFP) { > + MCE->emitByte(dwarf::DW_CFA_def_cfa_offset); > + } else { > + MCE->emitByte(...

...inal pass over the instructions and compute spill > // weights, coalesce virtual registers and remove identity moves > > ... > for (unsigned i = 0; i < mii->getNumOperands(); ++i) { > const MachineOperand& mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->SetMachineOperandReg(i, reg); > > Li...

...ass over the instructions and compute spill > // weights, coalesce virtual registers and remove identity moves > > ... > for (unsigned i = 0; i < mii->getNumOperands(); ++i) { > const MachineOperand& mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->SetMachineOperandReg(i, reg); > >...

Dear all, Here's a new patch with Evan's comments (thx Evan!) and some cleanups. Now the (duplicated) exception handling code is in a new file: lib/ExecutionEngine/JIT/JITDwarfEmitter. This patch should work on linux/x86 and linux/ppc (tested). Nicolas -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: jit-exceptions.patch URL:

...for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); > mbbi != mbbe; ++mbbi) { > [...] > > for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { > const MachineOperand &mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->getOperand(i).setReg(reg); > > Doesn't that las...

...used twice or more in an instruction, it only needs one > /// physical register. > std::set<unsigned> seen_regs; > for(unsigned u = 0; u < mi->getNumOperands(); u++) { > const MachineOperand & mo = mi->getOperand(u); > if(mo.isUse() && mo.isRegister() && mo.getReg()) { > if(MRegisterInfo::isVirtualRegister(mo.getReg())) { > unsigned v_reg = mo.getReg(); > if(this->vrm->hasStackSlot(v_reg)) { > int slot = this->vrm->getStackSlot(v_reg); > // First, try to fold t...

...eFunction::iterator mbbi = mf_->begin(), mbbe = mf_- > >end(); > mbbi != mbbe; ++mbbi) { > [...] > > for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { > const MachineOperand &mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->getOperand(i).setReg(reg); > > Doesn't that...