Displaying 20 results from an estimated 64 matches for "isreg".
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2016 Nov 21
2
Conditional jump or move depends on uninitialised value(s)
...error is at this line:
https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/DeadMachineInstructionElim.cpp#L142
Here I've refactored the code into a minimal (noinline) function that
still triggers the problem. xfunc2() and xfunc3() are also noinline.
The problem goes away if either isReg() or isDef() is marked noinline.
void xfuncx(const MachineOperand &MO,
const TargetRegisterInfo *TRI,
BitVector &LivePhysRegs) {
if (MO.isReg() && // <<<<------ problem reported here
MO.isDef()) {
xfunc2(MO, TRI, LivePhysRegs);
} else {...
2016 Nov 22
2
Conditional jump or move depends on uninitialised value(s)
...ow builds a MachineOperand that prints like this:
>
> <BB#2>
>
> The bottom word of this MachineOperand now looks like this, with
> (according to Valgrind) the x's corresponding to uninitialized bits:
>
> xxxx xxxx xxxx 0000 0000 0000 0000 0100
>
> At this point isReg() can be called safely since it looks only at the
> lower bits. isDef() cannot be called safely because it looks at bit 25.
> However it is clear that the C++ code (below) never calls isDef() when
> isReg() returns false, as it does here.
>
> So now back to the asm:
>
> 00000...
2012 Oct 29
3
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...MachineOperandType)OpKind; }
>
> - unsigned char getTargetFlags() const { return TargetFlags; }
> - void setTargetFlags(unsigned char F) { TargetFlags = F; }
> - void addTargetFlag(unsigned char F) { TargetFlags |= F; }
> + unsigned char getTargetFlags() const {
> + return isReg() ? 0 : TargetFlags;
> + }
> + void setTargetFlags(unsigned char F) {
> + assert(!isReg() && "Register operands can't have target flags");
> + TargetFlags = F;
> + }
> + void addTargetFlag(unsigned char F) {
> + assert(!isReg() && &quo...
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...hat encodes the
immediate in an extra instruction slot (what we call a constant
extended instruction).
We can encode that with a target flag on the immediate machine
operand. So the patch you quoted is not a problem.
The quoted patch only prohibits the use of flags on register operands
(that is MO.isReg()==true) because some of the code in CodeGen that
deals with register operands does not appropriately handle target
flags on the register operand (it might not transfer the information
from an "old" operand to an "updated" operand).
I guess I am asking you to clarify what you m...
2011 Jan 18
2
[LLVMdev] Dwarf info for byref register variables
...Decode the original location, and use that as the start of the byref
// variable's location.
const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false);
DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
if (Location.isReg()) {
if (Reg < 32)
addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg);
else {
Reg = Reg - dwarf::DW_OP_reg0;
addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg);
addUInt(Block, 0, dwarf::DW_FORM_udata, Reg);
}
} else {
if (Reg...
2016 May 09
2
Replacing an instruction in a post-RA pass
...cBlock& MBB = *MFI;
MachineInstr& MI = *II;
DebugLoc DL = MI.getDebugLoc();
MachineOperand& reg1 = MI.getOperand(0);
MachineOperand& reg2 = MI.getOperand(1);
MachineOperand& reg3 = MI.getOperand(2);
if(reg1.isReg() && reg2.isReg() && reg3.isReg()){
if((reg1.getReg()-8)%4 == (reg3.getReg()-8)%4){
MachineBasicBlock::instr_iterator NII = std::next(II);
//conflict if reg1 and reg3 are in same bank
errs() << "Conflict: &quo...
2016 Nov 27
5
Extending Register Rematerialization
...sAnalysis *aa) {
if(TII.isReMaterializablePossible(*DefMI, aa))
return false;
DEBUG(dbgs() << " ComplexRemat MI: " << *DefMI);
for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = DefMI->getOperand(i);
if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
continue;
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
if (MRI.isConstantPhysReg(MO.getReg(),
*DefMI->getParent()->getParent()))
continue;
//If not constant then check its def
if(depth > 6)
retur...
2015 Oct 23
3
[AMDGPU] AMDGPUAsmParser fails to parse several instructions
...ib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1085:43
...
The second line of the assembly has the assertion fail:
llvm-mc:
/mnt/dm-0/codebase/Compilers/LLVM/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:184:
void (anonymous namespace)::AMDGPUOperand::setModifiers(unsigned int):
Assertion `isReg()' failed.
and reports that 0.5 is "error: invalid operand for instruction"
v_mad_f32 v9, 0.5, v5, -v8
^
Regards,
李弘宇 (Li, Hong-Yu)
Department of Computer Science & Information Engineering
National Taiwan University
-------------- next part -----------...
2015 Oct 24
2
[AMDGPU] AMDGPUAsmParser fails to parse several instructions
...ate.
> >
> > The second line of the assembly has the assertion fail:
> >
> > llvm-mc:
> /mnt/dm-0/codebase/Compilers/LLVM/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:184:
> void (anonymous namespace)::AMDGPUOperand::setModifiers(unsigned int):
> Assertion `isReg()' failed.
> >
> > and reports that 0.5 is "error: invalid operand for instruction"
> >
> > v_mad_f32 v9, 0.5, v5, -v8
>
> There is a bug with operand parsing when you have immediate operands and
> source modifiers. I haven’t fixed this yet, but you ca...
2012 Oct 29
2
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...n extra instruction slot (what we call a constant
> extended instruction).
> We can encode that with a target flag on the immediate machine operand.
> So the patch you quoted is not a problem.
>
> The quoted patch only prohibits the use of flags on register operands
> (that is MO.isReg()==true) because some of the code in CodeGen that
> deals with register operands does not appropriately handle target flags
> on the register operand (it might not transfer the information from an
> "old" operand to an "updated" operand).
>
> I guess I am asking...
2017 Aug 22
5
[RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
Patch for review.
On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com>
wrote:
> Ping.
>
> Still working on preparing code for review. Will have a patch for review
> ready in the coming days.
>
> PL
>
> On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com>
> wrote:
>
>> Hi,
>>
>>
>>
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...kill>; dbg:../src/getbits.c:60:1
# End machine code for function CGA_kernel_read.
llc: /work/llvm/trunk/llvm/include/llvm/CodeGen/MachineRegisterInfo.h:76: static llvm::MachineOperand* llvm::MachineRegisterInfo::getNextOperandForReg(const llvm::MachineOperand*): Assertion `MO && MO->isReg() && "This is not a register operand!"' failed.
Program received signal SIGABRT, Aborted.
0xb7fdd424 in __kernel_vsyscall ()
(gdb) bt
#0 0xb7fdd424 in __kernel_vsyscall ()
#1 0xb7cfe1ef in __GI_raise (sig=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64
#2 0xb7d01835 in __...
2012 Jan 25
0
[LLVMdev] [PATCH] TLS support for Windows 32+64bit
On Thu, Jan 19, 2012 at 9:24 AM, Kai <kai at redstar.de> wrote:
> Hi!
>
> I added 2 more tests and also refined an assert statement. Applies cleanly
> to r148473 now. Are there more comments on the code? Thank you!!
+ assert(Inst.getOperand(0).isReg() &&
+ (Inst.getOperand(ImmOp).isImm() ||
+ (Inst.getOperand(ImmOp).isExpr() &&
+ Inst.getOperand(ImmOp).getExpr()->getKind() == MCExpr::SymbolRef) &&
+ static_cast<const
MCSymbolRefExpr*>(Inst.getOperand(ImmOp).getExpr())->getKind() ==
MCSymbolRefEx...
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...form complex boolean expressions.
To better understand how these new predicates work, let's have a look at the
following example.
```
def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() ==
AArch64::BLR &&
MI->getOperand(0).isReg() &&
MI->getOperand(0).getReg() !=
AArch64::LR}]>;
```
This tablegen code snippet has been taken from
AArch64/AArch64SchedExynosM3.td
Predicate `M3BranchLinkFastPred` can be rewritten using an...
2011 Sep 26
1
[LLVMdev] distinguishing between real arguments and variable arguments
...2>& RegUses)
{
switch(MI->getOpcode()) {
default: llvm_unreachable("Unknown opcode.");
case SP::CALL: break;
case SP::JMPLrr:
case SP::JMPLri:
assert(MI->getNumOperands() >= 2);
const MachineOperand &Reg = MI->getOperand(0);
assert(Reg.isReg() && "JMPL first operand is not a register.");
assert(Reg.isUse() && "JMPL first operand is not a use.");
RegUses.insert(Reg.getReg());
const MachineOperand &RegOrImm = MI->getOperand(1);
if (RegOrImm.isImm())
break;
asse...
2012 Jan 19
2
[LLVMdev] [PATCH] TLS support for Windows 32+64bit
Hi!
I added 2 more tests and also refined an assert statement. Applies
cleanly to r148473 now. Are there more comments on the code? Thank you!!
Regards
Kai
On 01.01.2012 22:01, Eli Friedman wrote:
> On Sun, Jan 1, 2012 at 10:44 AM, Kai<kai at redstar.de> wrote:
>> Happy new year to all!
>>
>> The attached patch adds TLS support for x86_64-pc-win32 and x86-pc-win32.
2010 Nov 05
0
[LLVMdev] Basic block liveouts
...std::vector<unsigned> liveout;
for( MachineBasicBlock::iterator mbbi = mbb->begin(), mbbe = mbb->end();
mbbi != mbbe; ++mbbi ) {
for( opi = 0, ope = mbbi->getNumOperands(); opi < ope; ++opi ) {
MachineOperand & operand = mbbi->getOperand(opi);
if( operand.isReg() == false )
continue;
if( operand.getReg() == 0 )
continue;
if( ! TargetRegisterInfo::isVirtualRegister(operand.getReg()) )
continue;
if( mbb != operand.getNextOperandForReg()->getParent()->getParent() )
liveout.push_back( operand.getReg() );...
2010 Jul 07
0
[LLVMdev] LLC Bug x86 with thread local storage
...to remove this $ character?
I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
O << '%' << getRegisterName(Op.getReg());
} else if (Op.isImm()) {
...
} else {
assert(Op.isExpr() && "unknown operand kind in printOperand");
// HERE I remove the '$' to make it work
O << '$' << *Op.ge...
2013 Oct 01
5
[LLVMdev] JIT compiler on ARM issue
Hello all,
When using the JIT on ARM, I get the following error message. The code works fine on both X86 32 and 64 bit architectures.
rbx: /home/dirkjan/llvm-3.3.src/include/llvm/CodeGen/MachineOperand.h:260: unsigned int llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.
Program received signal SIGABRT, Aborted.
[Switching to Thread 0x74fff460 (LWP 652)]
__libc_do_syscall () at ../ports/sysdeps/unix/sysv/linux/arm/eabi/libc-do-syscall.S:47
47 ../ports/sysdeps/unix/sysv/linux/arm/eabi/libc-do-sys...
2015 Aug 11
3
Working with X86 registers in MachineInstr
...en/kill sets for machine basic blocks. To start with, I am only
considering the general-purpose registers, RAX-R15 and their sub-registers.
Thus, I need to examine each MachineInstr to determine which register(s) it
defines and/or uses.
I see in the Doxygen that for a MachineOperand, I can call isReg() and
getReg() to figure out which X86 register the operand corresponds to. These
return an unsigned int "register number"; but I'm not sure how to identify
which register actually corresponds to that number.
Also, I will need to identify definitions and uses of registers in
instr...