search for: ispredicated

...; + // *** Must match HexagonBaseInfo.h *** >> + Type HexagonType = type; >> + let TSFlags{4-0} = HexagonType.Value; >> + bits<1> isHexagonSolo = 0; >> + let TSFlags{5} = isHexagonSolo; >> >> // Predicated instructions. >> bits<1> isPredicated = 0; >> - let TSFlags{1} = isPredicated; >> + let TSFlags{6} = isPredicated; >> >> // *** The code above must match HexagonBaseInfo.h *** >> } >> @@ -47,17 +64,25 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, >>...

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we

Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this

...nst<(outs), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) jumpr:t $src2", []>, Requires<[HasV3T]>; Its new definition would be like this: let Defs = [PC], isPredicated = 1 in class V3_J2_jumprfnewpt<list<dag> P = [], string C = ""> : JRInst <(outs), (ins PredRegs:$Pu, IntRegs:$Rs), "if (!$Pu.new) jumpr:t $Rs", P, C> { bits<2> Pu; bits<5> Rs; IClass = 0b0101; Inst{27-21} = 0...

...pBreaker.cpp (working copy) @@ -399,7 +399,7 @@ unsigned Reg = MO.getReg(); if (Reg == 0) continue; // Ignore KILLs and passthru registers for liveness... - if (MI->isKill() || (PassthruRegs.count(Reg) != 0)) + if (MI->isKill() || (PassthruRegs.count(Reg) != 0) || TII->isPredicated(MI)) continue; // Update def for Reg and aliases.

Forgive me if these questions are naive or if I'm misunderstanding something. I'm certainly very interested in seeing the MachineCopyPropagation patch finally land and stick. 1. Wouldn't function live-ins and reserved registers have started life as physical registers already? For example, wouldn't a live-in be a copy from a physical register to a virtual one allowing the flag to

Hello, The function ARMBaseInstrInfo::AnalyzeBranch contains the following piece of code: } else if (I->isReturn()) { // Returns can't be analyzed, but we should run cleanup. CantAnalyze = !isPredicated(I); } else { This could lead to cases where for a block that ends with a conditional return, AnalyzeBranch returns false (i.e. analyzed), both TBB and FBB are nullptr, and Cond is empty, that is, indicating no branches at all. Since returns do not have any additional CFG edges correspondin...

Thank you for your reply! > Every MachineBasicBlock has a list of successors; you can access it with > the successors() accessor. That's what you should be using for any CFG > analysis. I am aware of these methods of class MachineBasicBlock, which allows one to access a MachineBasicBlock's successors and predecessors in the CFG. But the CFG itself may no longer be valid if a