Displaying 4 results from an estimated 4 matches for "ispredicable".
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...default:
>> + return false;
>> + }
>> +}
>> +
>> +bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
>> + return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
>> +}
>>
>> bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
>> bool isPred = MI->getDesc().isPredicable();
>> @@ -559,6 +1414,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
>>
>> unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
>> switch(Opc...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...Register coalescer
or the allocator ?
@Jakob: I noticed your commit last week regarding
TRI::getCommonSuperRegClass(). Can that have a role to play here?
FWIW, the relevant patterns for COMBINE_rr are shown below.
------------------------------------------------------------------
// Combine.
let isPredicable = 1, neverHasSideEffects = 1 in
def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = combine($src1, $src2)",
[]>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),...
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
...memoperands_empty()) when lowered via this pattern. This causes the
loads to be volatile and "unpacketizable".
Is there no way to preserve or attach MemRefs to the LDriw instructions
generated by way of a pattern in the InstrInfo.td file ? FWIW, the LDriw
instruction is as show here.
let isPredicable = 1 in
def LDriw : LDInst<(outs IntRegs:$dst),
(ins MEMri:$addr), "$dst = memw($addr)",
[(set IntRegs:$dst, (i32 (load ADDRriS11_2:$addr)))]>;
TIA,
Pranav
Qualcomm Innovation Center, (QuIC) is a member of the Code Aurora Forum.
2008 Apr 27
2
[LLVMdev] Questions for new Backend
...bit mayLoad = 0;
bit mayStore = 0;
bit isTwoAddress = 0; // see question 1
bit isConvertibleToThreeAddress = 0; // see question 1
bit isCommutable = 0; // see rq1 below
bit isTerminator = 0; // terminate what? A BB, A function, or the
program
bit isReMaterializable = 0; // ?
bit isPredicable = 0;
bit hasDelaySlot = 0;
bit usesCustomDAGSchedInserter = 0;
bit hasCtrlDep = 0; // ?
bit isNotDuplicable = 0; // ?
bit hasSideEffects = 0;
bit mayHaveSideEffects = 0; // how is this different from has side effect?
bit neverHasSideEffects = 1;
Rq1: If I have a instruction 'add...