Displaying 7 results from an estimated 7 matches for "ispostra".
2016 Jan 17
2
Need help with changes to 'ScheduleDAGInstrs' on the v3.8 branch
...#257626). This is currently working on
the v3.7.1 sources, but the changes to 'llvm::ScheduleDAGInstrs' have me
stumped as to how to revise my implementation to track the changes to this
class.
Our 'SHAVEAsmScheduler' derives from 'ScheduleDAGInstrs' and uses both the
'IsPostRA' and 'LiveIntervals' that were in 'ScheduleDAGInstrs', but which
have now been removed.
Are there any guidelines as to how implementations such as ours which are
still using a legacy scheduling model should be migrated to whatever the
preferred scheduling model is? I expect th...
2016 Oct 28
2
mischeduler
...ctually done once per cycle, in contrast to what the comment
suggests.
...
// Schedule aggressively for latency in PostRA mode. We don't check for
// acyclic latency during PostRA, and highly out-of-order processors will
// skip PostRA scheduling.
if (!OtherResLimited) {
if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() >
Rem.CriticalPath)) {
Policy.ReduceLatency |= true;
Why !OtherResLimited? tryCandidate() has already checked for resource
balancing just
before this. To not do the latency check then only means falling back to
original
order.
/Jonas
2018 Jan 17
1
Checking when Register Allocation has been performed
> On Jan 16, 2018, at 11:31 PM, Martin J. O'Riordan <MartinO at theheart.ie> wrote:
>
> Thanks Matthias,
>
> I have both a pre-RA and a post-RA scheduler, and I had thought that I could track “has RA happened?” by setting a flag in my pre-RA scheduler as it completes - my suspicion (which you have confirmed) was that “#vregs == 0” was not a safe assumption. What I
2012 Mar 29
2
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
..., SUnit * SUJ);
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit * SUJ);
};
R600Packetizer::R600Packetizer(MachineFunction &MF, MachineLoopInfo &MLI,
MachineDominatorTree &MDT, LiveIntervals * LIS) :
VLIWPacketizerList(MF, MLI, MDT, false /* isPostRA */, LIS) { }
bool R600Packetizer::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ)
{
return true;
}
bool R600Packetizer::isLegalToPruneDependencies(SUnit *SUI, SUnit * SUJ)
{
return false;
}
class R600PacketizeInstrsPass : public MachineFunctionPass {
public:
static char ID;
R600Pack...
2018 Jan 15
0
Checking when Register Allocation has been performed
Maybe
MF.getProperties().hasProperty(MachineFunctionProperties::Property::NoVRegs))?
~Craig
On Mon, Jan 15, 2018 at 12:07 PM, Martin J. O'Riordan via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi LLVM Devs,
>
>
>
> I have some shared code that performs lowering operations that can occur
> before or after register allocation. When it is pre-RA I want to only use
2018 Jan 15
3
Checking when Register Allocation has been performed
Hi LLVM Devs,
I have some shared code that performs lowering operations that can occur
before or after register allocation. When it is pre-RA I want to only use
virtual registers for intermediate results, but post-RA I have to use only a
very restricted set of physical registers.
Code generation using the restricted set is not as efficient as it is when I
can use virtual registers. At
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...s
>> // Schedule method to build the dependence graph.
>> class DefaultVLIWScheduler : public ScheduleDAGInstrs {
>> public:
>> DefaultVLIWScheduler(MachineFunction&MF, MachineLoopInfo&MLI,
>> - MachineDominatorTree&MDT, bool IsPostRA);
>> + MachineDominatorTree&MDT, bool IsPostRA);
>> // Schedule - Actual scheduling work.
>> void schedule();
>> };
>> -} // end anonymous namespace
>> +}
>>
>> DefaultVLIWScheduler::DefaultVLIWScheduler(
>>...