search for: isphysreg

Displaying 2 results from an estimated 2 matches for "isphysreg".

2016 Jan 22
2
Allowing virtual registers after register allocation
...eIns.push_back(RegisterMaskPair(PhysReg, LaneMask)); > } > > this needs to be changed to support VRegs. But if we do that change, I'd like to change it to something like this: > > void addLiveIn(unsigned Reg, LaneBitmask LaneMask = ~0u) { > assert(TargetRegisterInfo::isPhysReg(Reg) || getParent()->getRegInfo().getVirtRegsAfterRegalloc()); > LiveIns.push_back(RegisterMaskPair(Reg, LaneMask)); > } I haven’t looked at the patch, just commenting on that example. My understanding was that supporting both virtual and physical registers should not have any impac...
2016 Jan 22
2
Allowing virtual registers after register allocation
Here are 2 patches, which are independent of each other. The first splits PrologEpilogInserter into 2 parts : http://reviews.llvm.org/D16481 After looking at the code I thought it made more sense for the major split to include whether callee-saved register spills are supported. So for non-virtual targets, virtual registers are not supported and scavenging is optionally supported, and vice versa