Displaying 6 results from an estimated 6 matches for "ismclass".
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2011 Aug 30
2
[LLVMdev] cortex-m{3,4} special registers
...h as "IsThumb2".
Generally this is fine, however MRS has different encodings in v{6,7}m and
v{6,7}{a,r} - the encodings are not sufficiently different to deterministically
tell them apart without subtarget specific information.
I can encode that as instruction predicates (, Requires<[IsMClass]>, assuming
I've added a new predicate 'IsMClass'), but getting the generated decoder to be
subtarget-dependent was quite an invasive change. I also had to do the same with
the MCInstPrinter - it can't know whether to print mask names for the M-series
or the AR-series without a S...
2011 Aug 31
0
[LLVMdev] cortex-m{3,4} special registers
...;
> Generally this is fine, however MRS has different encodings in v{6,7}m and
> v{6,7}{a,r} - the encodings are not sufficiently different to deterministically
> tell them apart without subtarget specific information.
>
> I can encode that as instruction predicates (, Requires<[IsMClass]>, assuming
> I've added a new predicate 'IsMClass'), but getting the generated decoder to be
> subtarget-dependent was quite an invasive change. I also had to do the same with
> the MCInstPrinter - it can't know whether to print mask names for the M-series
> or the A...
2011 Aug 29
0
[LLVMdev] cortex-m{3,4} special registers
Hi Kurt,
The assembly parser doesn't (yet) handle these, you're right. Currently, the MRS instruction is split into two variants in the ARMInstrThumb2.td file, t2MRS and t2MRSsys, one for the user mode version reading cpsr and one for the system mode version reading spsr. MSR, by contrast, has a custom parse method for the mask operand since it's a bit more complex than an either/or.
2011 Aug 28
2
[LLVMdev] cortex-m{3,4} special registers
I was attempting to compile some code with a recent (r138716)
version of llvm/clang, targeting a cortex-m4 processor.
And I get an error like this:
CC: sched_garbage.c
In file included from sched_garbage.c:43:
In file included from ./os_internal.h:48:
In file included from /p/nuttx/trunk/nuttx/include/sched.h:47:
In file included from /p/nuttx/trunk/nuttx/include/nuttx/sched.h:54:
In file
2014 Jun 19
2
[LLVMdev] [PATCH] triples for baremetal
..., Triple::Win32)
Index: lib/Target/ARM/ARMSubtarget.cpp
===================================================================
--- lib/Target/ARM/ARMSubtarget.cpp (revision 211122)
+++ lib/Target/ARM/ARMSubtarget.cpp (working copy)
@@ -264,7 +264,7 @@
default:
if ((isTargetIOS() && isMClass()) ||
(TargetTriple.isOSBinFormatMachO() &&
- TargetTriple.getOS() == Triple::UnknownOS))
+ TargetTriple.getOS() == Triple::NoneOS))
TargetABI = ARM_ABI_AAPCS;
else
TargetABI = ARM_ABI_APCS;
Index: unittests/ADT/TripleTest.cpp
========...
2014 Jun 17
4
[LLVMdev] triples for baremetal
[+llvmdev, -llvm-dev]
(Oopsies, llvmdev doesn't have a hyphen in it like all the others do)
On 6/17/14, 10:45 AM, Jonathan Roelofs wrote:
> [+llvm-dev, cfe-dev]
>
> Was "Re: [PATCH] ARM: allow inline atomics on Cortex M"
>
> On 6/17/14, 10:42 AM, Jonathan Roelofs wrote:
>>
>>
>> On 6/17/14, 9:35 AM, Renato Golin wrote:
>>> On 17 June 2014