search for: islegalmaskedgath

...2016). More exactly: - do you envision to support in the near future LLVM IR gather and scatter intrinsics (as described at http://llvm.org/docs/LangRef.html#llvm-masked-gather-intrinsics and scatter)? I see you have defined some methods that should use them like: - bool isLegalMaskedGather(Type *DataType); - void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr) which defines a bool CreateGatherScatter, etc I gave to clang a simple vector add C program with step/stride 2 with flag "-avx2", but the resulting vector code does NOT use gath...

...Sanjay Patel <spatel at rotateright.com> wrote: > I was just looking at the related masked load/store operations, and I > think there are at least 2 bugs: > > 1. X86TTIImpl::isLegalMaskedLoad/Store() should be legal for FP types with > AVX1 (not just AVX2). > 2. X86TTIImpl::isLegalMaskedGather/Scatter() should be legal for 128/256 > bit vectors with AVX2 (not just AVX512). > > I looked at this for the first time today, so I may be missing something... > > So for the moment, the answer to your question is 'no'; there's no generic > way to produce these inst...

...ese under Analysis subtree (instead of Transform), since they are indeed Analysis. As a first step of this LoopVectorizationLegality cleanup, I propose to move the following checks (and member functions) to LoopVectorizationCostModel. isLegalMaskedStore isLegalMaskedLoad isLegalMaskedScatter isLegalMaskedGather My assumption is that all SIMD architectures should support serialization of those operations at some cost (e.g., lowering in CG prepare) and thus failing to vectorize due to "false" return values of those calls is incorrect behavior. I'll make sure to use a very high initial cost...

Hi, I used clang -O3 -c -emit-llvm on the follow code to generate a bitcode, say a.bc. I read the .ll file and didn't see any gather intrinsic. Also, I used opt -O3 -mcpu=core-avx2/-mcpu=skx, but there is still no gather intrinsic generated. int foo(int A[800], int B[800], int C[800]) { for (int i = 0; i < 800; i++) { A[B[i]] = i + 5; } for (int i = 0; i < 800;

...ad of Transform), since they are indeed Analysis. > > As a first step of this LoopVectorizationLegality cleanup, I propose to move the following checks > (and member functions) to LoopVectorizationCostModel. > isLegalMaskedStore > isLegalMaskedLoad > isLegalMaskedScatter > isLegalMaskedGather > My assumption is that all SIMD architectures should support serialization of those operations > at some cost (e.g., lowering in CG prepare) and thus failing to vectorize due to "false" return values > of those calls is incorrect behavior. I'll make sure to use a very hig...

...d of Transform), since they are indeed Analysis. > > As a first step of this LoopVectorizationLegality cleanup, I propose > to move the following checks (and member functions) to LoopVectorizationCostModel. > isLegalMaskedStore > isLegalMaskedLoad > isLegalMaskedScatter > isLegalMaskedGather > My assumption is that all SIMD architectures should support > serialization of those operations at some cost (e.g., lowering in CG > prepare) and thus failing to vectorize due to "false" return values of > those calls is incorrect behavior. I'll make sure to use a...

...y are indeed Analysis. >> >> As a first step of this LoopVectorizationLegality cleanup, I propose >> to move the following checks (and member functions) to LoopVectorizationCostModel. >> isLegalMaskedStore >> isLegalMaskedLoad >> isLegalMaskedScatter >> isLegalMaskedGather >> My assumption is that all SIMD architectures should support >> serialization of those operations at some cost (e.g., lowering in CG >> prepare) and thus failing to vectorize due to "false" return values of >> those calls is incorrect behavior. I'll make s...

...are indeed Analysis. >> >> As a first step of this LoopVectorizationLegality cleanup, I propose >> to move the following checks (and member functions) to LoopVectorizationCostModel. >> isLegalMaskedStore >> isLegalMaskedLoad >> isLegalMaskedScatter >> isLegalMaskedGather >> My assumption is that all SIMD architectures should support >> serialization of those operations at some cost (e.g., lowering in CG >> prepare) and thus failing to vectorize due to "false" return values >> of those calls is incorrect behavior. I'll make...

Hi, > On Apr 22, 2016, at 8:27 PM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Rob, > > The problem here is that the d[i] array is only conditionally accessed, and so we can't if-convert the loop body. The compiler does not know that d[i] is actually dereferenceable for all i from 0 to 15 (the array might be shorter and p[i] is 0 for i past the end

...el <spatel at rotateright.com<mailto:spatel at rotateright.com>> wrote: I was just looking at the related masked load/store operations, and I think there are at least 2 bugs: 1. X86TTIImpl::isLegalMaskedLoad/Store() should be legal for FP types with AVX1 (not just AVX2). 2. X86TTIImpl::isLegalMaskedGather/Scatter() should be legal for 128/256 bit vectors with AVX2 (not just AVX512). I looked at this for the first time today, so I may be missing something... So for the moment, the answer to your question is 'no'; there's no generic way to produce these instructions. You should be able...