Displaying 6 results from an estimated 6 matches for "isinlineasm".
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inlineasm
2015 Jan 02
3
[LLVMdev] "ran out of registers during register allocation"
I'm getting this error in RegAllocFast.cpp in compiling one source file
in test-suite as the result of a new Mips fast-isel patch
I was testing.
It apparently just generates bad code and continues?
// Nothing we can do. Report an error and keep going with a bad
allocation.
if (MI->isInlineAsm())
MI->emitError("inline assembly requires more registers than
available");
else
MI->emitError("ran out of registers during register allocation");
How is it possible to run out of registers during register allocation? Lol.
Reed
2015 Jan 03
2
[LLVMdev] "ran out of registers during register allocation"
...rce
>> file in test-suite as the result of a new Mips fast-isel patch
>> I was testing.
>>
>> It apparently just generates bad code and continues?
>>
>> // Nothing we can do. Report an error and keep going with a bad
>> allocation.
>> if (MI->isInlineAsm())
>> MI->emitError("inline assembly requires more registers than
>> available");
>> else
>> MI->emitError("ran out of registers during register allocation");
>>
>>
>> How is it possible to run out of registers during re...
2016 Nov 27
5
Extending Register Rematerialization
...ister(DefReg))
return false;
// Avoid instructions obviously unsafe for remat.
if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects())
return false;
// Don't remat inline asm. We have no idea how expensive it is
// even if it's side effect free.
if (MI.isInlineAsm())
return false;
}
We have following doubts and require guidance and suggestion to move ahead:
1. Is the approach we are following feasible?
2. What will be the suitable method to store the sequence of instruction
for recomputing value which will be used during transformation.
3. Suggestion fo...
2013 Jul 16
1
[LLVMdev] Instantiating Target-Specifc ASM Parser
Hello,
I am working on backend development and would like to utilize my target's MCAsmParser inside of an MCInst-level class implementation. I noticed that the AsmParser is registered with the target registry however I am having no luck grepping for a "template" of how to instantiate it and have yet to find specific documentation on how it is done. Any ideas or help is greatly
2017 Oct 26
3
RFC: Adding bit to register MachineOperands to allow post-RA register renaming
Forgive me if these questions are naive or if I'm misunderstanding
something. I'm certainly very interested in seeing the
MachineCopyPropagation patch finally land and stick.
1. Wouldn't function live-ins and reserved registers have started life as
physical registers already? For example, wouldn't a live-in be a copy from
a physical register to a virtual one allowing the flag to
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...ary(MI, MBB, MF))
>> - return true;
>> -
>> - return false;
>> -}
>> -
>> -// isSoloInstruction - return true if instruction I must end previous
>> -// packet.
>> -bool VLIWPacketizerList::isSoloInstruction(MachineInstr *I) {
>> - if (I->isInlineAsm())
>> - return true;
>> -
>> - return false;
>> -}
>> + if (VLIWScheduler)
>> + delete VLIWScheduler;
>>
>> -// addToPacket - Add I to the current packet and reserve resource.
>> -void VLIWPacketizerList::addToPacket(MachineInstr *MI) {...