Displaying 7 results from an estimated 7 matches for "isimp".
Did you mean:
simp
2015 Apr 28
2
[LLVMdev] RFC: Machine Level IR text-based serialization format
...e this:
- The IsDef flag is implied by the use of the register before the '=',
unless it's implicit.
- TiedTo and IsEarlyClobber aren't not serialized, as they are defined by
the instruction description. (I believe that's true in all cases, but I'm
not 100% sure).
- IsUndef, IsImp, IsKill, IsDead, IsInternalRead, IsDebug - keywords like
'implicit', 'undef', 'kill', 'dead' are used before the register e.g.
'undef %rax', 'implicit-def kill %eflags'.
I don't have a syntax for the SubReg_TargetFlags at the moment.
Alex
>...
2012 Mar 30
1
[LLVMdev] load instruction memory operands value null
Hi,
For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.
For "load instruction", Machine Instruction dumps as below:
vr12<def> = LD_Iri %vr2<kill>, 0;
2012 Oct 29
3
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...er number, only valid for MO_Register. A
> value of 0
> + /// indicates the MO_Register has no subReg.
> + unsigned char SubReg;
> +
> + /// TargetFlags - This is a set of target-specific operand flags.
> + unsigned char TargetFlags;
> + };
>
> /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for
> MO_Register
> /// operands.
> @@ -176,9 +179,17 @@
> ///
> MachineOperandType getType() const { return
> (MachineOperandType)OpKind; }
>
> - unsigned char getTargetFlags() const { return TargetFlags; }
> - void...
2015 Apr 28
2
[LLVMdev] RFC: Machine Level IR text-based serialization format
...e of the register before the '=',
>> unless it's implicit.
>> - TiedTo and IsEarlyClobber aren't not serialized, as they are defined by
>> the instruction description. (I believe that's true in all cases, but I'm
>> not 100% sure).
>> - IsUndef, IsImp, IsKill, IsDead, IsInternalRead, IsDebug - keywords like
>> 'implicit', 'undef', 'kill', 'dead' are used before the register e.g.
>> 'undef %rax', 'implicit-def kill %eflags'.
>> I don't have a syntax for the SubReg_TargetFlags a...
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...er. A
>> value of 0
>> + /// indicates the MO_Register has no subReg.
>> + unsigned char SubReg;
>> +
>> + /// TargetFlags - This is a set of target-specific operand flags.
>> + unsigned char TargetFlags;
>> + };
>>
>> /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for
>> MO_Register
>> /// operands.
>> @@ -176,9 +179,17 @@
>> ///
>> MachineOperandType getType() const { return
>> (MachineOperandType)OpKind; }
>>
>> - unsigned char getTargetFlags() const { retu...
2012 Oct 29
2
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
.../// indicates the MO_Register has no subReg.
> >> + unsigned char SubReg;
> >> +
> >> + /// TargetFlags - This is a set of target-specific operand
> flags.
> >> + unsigned char TargetFlags;
> >> + };
> >>
> >> /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for
> >> MO_Register
> >> /// operands.
> >> @@ -176,9 +179,17 @@
> >> ///
> >> MachineOperandType getType() const { return
> >> (MachineOperandType)OpKind; }
> >>
> >> - uns...
2015 Apr 28
9
[LLVMdev] RFC: Machine Level IR text-based serialization format
Hi all,
I would like to propose a text-based, human readable format that will be used to
serialize the machine level IR. The major goal of this format is to allow LLVM
to save the machine level IR after any code generation pass and then to load
it again and continue running passes on the machine level IR. The
primary use case
of this format is to enable easier testing process for the code