Displaying 9 results from an estimated 9 matches for "ishorizontalbinop".
2014 Nov 11
4
[LLVMdev] supporting SAD in loop vectorizer
...kel at anl.gov>
> Cc: "Dibyendu Das" <Dibyendu.Das at amd.com>, llvmdev at cs.uiuc.edu
> Sent: Tuesday, November 11, 2014 8:21:37 AM
> Subject: Re: [LLVMdev] supporting SAD in loop vectorizer
>
>
> If you'd like to contribute support for this, look at
> isHorizontalBinOp and go from there. Feel free to ask questions if
> you get stuck.
>
>
>
> FWIW, I've looked at isHorizontalBinOp for inspiration for matching
> AArch64 ADDV-and-friends (horizontal reduction operations), and
> thought it was rather temperamental and noticed it being pron...
2014 Nov 11
3
[LLVMdev] supporting SAD in loop vectorizer
...he end looks like below where
> we see the icmp, neg select pattern appearing twice.
> Are we saying we pattern match this to PSADBW in target ?
Yes.
> That seems
> to have some challenges
It does, but we already have code in the backend that matches other horizontal operations (see isHorizontalBinOp and its callers in lib/Target/X86/X86ISelLowering.cpp), and I suspect this won't be significantly more complicated.
> including the fact that we would need a
> 4-way unroll to use all of 128b PSADBWs. Or am I
> missing something ?
No, each unrolling will get its own, so you'll ge...
2011 Sep 22
3
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
...o,
> Some comments:
>
> + // Try to synthesize horizontal adds from adds of shuffles.
> + if (((Subtarget->hasSSE3()&& (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
> + (Subtarget->hasAVX()&& (VT == MVT::v8f32 || VT == MVT::v4f64)))&&
> + isHorizontalBinOp(LHS, RHS, true))
>
> 1) You probably want to do something like:
>
> "bool HasHorizontalArith = Subtarget->hasSSE3() ||
> Subtarget->hasAVX()" and check it for the first condition, because
> when AVX is on, the SSE levels are all turned off (as to consider AVX
>...
2011 Sep 21
0
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
...egen bits.
This is awesome :D
Some comments:
+ // Try to synthesize horizontal adds from adds of shuffles.
+ if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
+ (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
+ isHorizontalBinOp(LHS, RHS, true))
1) You probably want to do something like:
"bool HasHorizontalArith = Subtarget->hasSSE3() ||
Subtarget->hasAVX()" and check it for the first condition, because
when AVX is on, the SSE levels are all turned off (as to consider AVX
a reimplementation of all SSE lev...
2011 Sep 22
0
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
...o,
> Some comments:
>
> + // Try to synthesize horizontal adds from adds of shuffles.
> + if (((Subtarget->hasSSE3()&& (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
> + (Subtarget->hasAVX()&& (VT == MVT::v8f32 || VT == MVT::v4f64)))&&
> + isHorizontalBinOp(LHS, RHS, true))
>
> 1) You probably want to do something like:
>
> "bool HasHorizontalArith = Subtarget->hasSSE3() ||
> Subtarget->hasAVX()" and check it for the first condition, because
> when AVX is on, the SSE levels are all turned off (as to consider AVX
>...
2011 Sep 21
2
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from floating
point additions and subtractions of appropriate vector shuffles. To do this I
introduced new x86 FHADD and FHSUB opcodes. These need to be wired up somehow
in the .td file to the appropriate instructions. Since I have no idea how
tablegen works I just hacked it in horribly. It works, but breaks support for
the hadd
2014 Nov 04
3
[LLVMdev] supporting SAD in loop vectorizer
----- Original Message -----
> From: "Renato Golin" <renato.golin at linaro.org>
> To: "Dibyendu Das" <Dibyendu.Das at amd.com>
> Cc: llvmdev at cs.uiuc.edu
> Sent: Tuesday, November 4, 2014 5:23:30 AM
> Subject: Re: [LLVMdev] supporting SAD in loop vectorizer
>
> On 4 November 2014 11:06, Das, Dibyendu <Dibyendu.Das at amd.com> wrote:
2013 Jul 26
0
[LLVMdev] Vector DAG Patterns
To elaborate, it is not only cumbersome writing these patterns for
vectors of 16 characters (v16i8), it does not work.
When I compile with this pattern for an andx operation on v16i8:
/[(set RC:$dst,//
// (and (i8 (vector_extract(vt VC:$src), 0 ) ), //
// (and (i8 (vector_extract(vt VC:$src), 1 ) ),//
// (and (i8 (vector_extract(vt VC:$src), 2 ) ),//
////(and (i8 (vector_extract(vt
2013 Jul 23
3
[LLVMdev] Vector DAG Patterns
Hi All,
Been having a problem constructing a suitable pattern to represent some
vector operations in the DAG. Stuff like andx/orx operations where
elements of a vector are anded/ored together.
My approach thus far has been to extract the sub elements of the vector
and and/or those elements. This is ok for 4 vectors of i32s, but becomes
cumbersome for v16i8s. Example instruction:
andx $dst