Displaying 2 results from an estimated 2 matches for "isfpimm".
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fpimm
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
...xup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {
unsigned Reg = MO.getReg();
unsigned RegNo = getMipsRegisterNumbering(Reg);
return RegNo;
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
} else if (MO.isFPImm()) {
return static_cast<unsigned>(APFloat(MO.getFPImm())
.bitcastToAPInt().getHiBits(32).getLimitedValue());
} else if (MO.isExpr()) {
const MCExpr *p_expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, p_expr,
MCFixupKind(Mips::fixup_Mips_Branch_PCRel)));...
2011 Oct 10
0
[LLVMdev] Adding fixups and relocations late in code generation
...rand &MO = MI.getOperand(OpNo);
>
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
>
> unsigned RegNo = getMipsRegisterNumbering(Reg);
> return RegNo;
>
> } else if (MO.isImm()) {
> return static_cast<unsigned>(MO.getImm());
> } else if (MO.isFPImm()) {
> return static_cast<unsigned>(APFloat(MO.getFPImm())
> .bitcastToAPInt().getHiBits(32).getLimitedValue());
> } else if (MO.isExpr()) {
> const MCExpr *p_expr = MO.getExpr();
> Fixups.push_back(MCFixup::Create(0, p_expr,
> MCFixupKind(Mips::fixup...