Displaying 11 results from an estimated 11 matches for "isfloattyp".
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isfloatty
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
...t(!i->saturate);
+ assert(!i->ftz);
+ emitNegAbs12(i);
+ if (i->op == OP_SUB)
+ code[0] ^= 1 << 8;
+}
+
+void
CodeEmitterNVC0::emitUADD(const Instruction *i)
{
uint32_t addOp = 0;
@@ -895,6 +947,8 @@ CodeEmitterNVC0::emitMINMAX(const Instruction *i)
else
if (!isFloatType(i->dType))
op |= isSignedType(i->dType) ? 0x23 : 0x03;
+ if (i->dType == TYPE_F64)
+ op |= 0x01;
emitForm_A(i, op);
emitNegAbs12(i);
@@ -2242,20 +2296,26 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- i...
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Pretty sure there's nothing wrong with it, but it looks odd in the code.
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++--
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
2016 Sep 30
2
[PATCH v2] nv50/ir: constant fold OP_SPLIT
...ivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -932,6 +932,22 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
Instruction *newi = i;
switch (i->op) {
+ case OP_SPLIT: {
+ uint8_t size = typeSizeof(i->dType);
+ DataType type = typeOfSize(size / 2, isFloatType(i->dType),
+ isSignedType(i->dType));
+ if (likely(type != TYPE_NONE)) {
+ uint64_t val = imm0.reg.data.u64;
+ uint16_t shift = size * 8;
+ bld.setPosition(i, false);
+ for (int8_t d = 0; i->defExists(d); ++d) {
+...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...+
if (i->src(0).mod.neg()) code[1] |= 0x04000000;
if (i->src(1).mod.neg()) code[1] |= 0x08000000;
if (i->src(0).mod.abs()) code[1] |= 0x00100000;
@@ -1725,7 +1793,9 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn->dType))
emitFADD(insn);
else if (insn->getDef(0)->reg.file == FILE_ADDRESS)
emitAADD(insn);
@@ -1733,14 +1803,18 @@ CodeEmitterNV50::emitInstructi...
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
..._target_nv50.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> @@ -413,6 +413,8 @@ TargetNV50::isOpSupported(operation op, DataType ty) const
> return false;
> case OP_SAD:
> return ty == TYPE_S32;
> + case OP_SET:
> + return !isFloatType(ty);
> default:
> return true;
> }
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
On 28.09.2016 02:01, Ilia Mirkin wrote:
> On Tue, Sep 27, 2016 at 7:25 PM, Tobias Klausmann
> <tobias.johannes.klausmann at mni.thm.de> wrote:
>> Split the source immediate value into two new values and create OP_MOV
>> instructions the two newly created values.
>>
>> Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
>> ---
2016 Sep 30
0
[PATCH] nv50/ir: constant fold OP_SPLIT
...o you think?
>
>
> Well with this you'd not set the new type right: bld.mkMov(def, val,
>>>type<<), where you always would use TYPE_U32. Not sure if that is what we
> want... other than that that, shorten it like this would be nice!
pah-shaw :(
typeOfSize(shift / 2, isFloatType(i->dType), isSignedType(i->dType))
How's that :p
>
>
>>
>>> + delete_Instruction(prog, i);
>>> + }
>>> + }
>>> + break;
>>> case OP_MUL:
>>> if (i->dType == TYPE_F32)
>>>...
2016 Sep 30
0
[PATCH v2] nv50/ir: constant fold OP_SPLIT
...phole.cpp
> @@ -932,6 +932,22 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> Instruction *newi = i;
>
> switch (i->op) {
> + case OP_SPLIT: {
> + uint8_t size = typeSizeof(i->dType);
> + DataType type = typeOfSize(size / 2, isFloatType(i->dType),
> + isSignedType(i->dType));
Er wait, sorry, I might have confused matters here...
Why do you need to compute type at all? Why not just reuse i->dType?
> + if (likely(type != TYPE_NONE)) {
> + uint64_t val = imm0.reg.data...
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before.
nothing really changed from the last version, just minor things.
Karol Herbst (5):
nv50/ir: restructure and rename postraconstantfolding pass
nv50/ir: implement mad post ra folding for nvc0+
gk110/ir: add LIMM form of mad
gm107/ir: add LIMM form of mad
nv50/ir: also do PostRaLoadPropagation for FMA
2015 Nov 05
7
[PATCH mesa 0/5] nouveau: codegen: Make use of double immediates
Hi All,
This series implements using double immediates in the nouveau codegen code.
This turns the following (nvc0) code:
1: mov u32 $r2 0x00000000 (8)
2: mov u32 $r3 0x3fe00000 (8)
3: add f64 $r0d $r0d $r2d (8)
Into:
1: add f64 $r0d $r0d 0.500000 (8)
This has been tested with the 2 double shader tests which I just send to
the piglet list. On a gk208 (gk110 / SM35)
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
Retrieving the high 32 bits of a signed multiply is rather annoying. It
appears that the simplest way to do this is to compute the absolute
value of the arguments, and perform a u32 x u32 -> u64 operation. If the
arguments' signs differ, then negate the result. Since there is no u64
support in the cvt instruction, we have the perform the 2's complement
negation "by hand".