search for: iselector

...cs (like comparisons which are not supported for address regs). Is it still possible to get ride of this with register classes ? I can make a pass before ISel to annotate the code identifying those registers which are only used for addressing (by doing a simple data-flow analysis), can it help ISelector later ? Because I could not find how to get metadata from the DAG to drive matching rules or lowering phases, is it possible ? How is metadata transferred to the DAG, where should I look for it ? Ivan >> Moreover, the standard pointer arithmetic is not >> enough for us (we need to s...

...t either register class should have a variant for each. ISel will choose the appropriate one based on the rest of the operands. > I can make a pass before ISel to annotate the code identifying those registers which are only used for addressing (by doing a simple data-flow analysis), can it help ISelector later ? > Because I could not find how to get metadata from the DAG to drive matching rules or lowering phases, is it possible ? How is metadata transferred to the DAG, where should I look for it ? > Metadata should not be necessary for this. In general, metadata should never be used for an...

...OPC_EmitConvertToTarget, 1, /*3307*/ OPC_EmitNodeXForm, 0, 3, // XLoadImm ... AADDMri supersedes DADDri (the same checks are performed). It's worth to note that the result is used by another instruction which has LSubRegs as its source operand and I got copy instructions added by the iselector to meet this requirement. I really would like to know why this is happening. It's like tblgen is not taking into account the register class assignations of both instructions :-/. Ivan >> I can make a pass before ISel to annotate the code identifying those registers which are only use...

...ngs sane. > /*3307*/ OPC_EmitNodeXForm, 0, 3, // XLoadImm > ... > > AADDMri supersedes DADDri (the same checks are performed). It's worth to note that the result is used by another instruction which has LSubRegs as its source operand and I got copy instructions added by the iselector to meet this requirement. Hmm.. OK. So it's correctly understanding the class requirements of the instruction, just not doing what we want in order to meet them. I'm suspecting TableGen isn't as ambitious as one would hope in this regard. That is, defining separate instructions w/ the...

...IntRegs:$b), "muladd $a, $b, $dst", [(set (i32 IntRegs:$dst), (mula_pat (v2i16 IntRegs:$a), (v2i16 IntRegs:$b)))]>; IntRegs is class with a type list of [i32, v2i16] But I get the following error when llvm building system try to generate the ISelector llvm[3]: Building Sparc.td DAG instruction selector implementation with tblgen vtInt: (vt:Other)<<P:Predicate_vtInt>> Type constraint application shouldn't fail!0 llvm-tblgen 0x081d6de7 1 llvm-tblgen 0x081d6b74 2 0x4001d400 __kernel_sigreturn + 0 3 libc.so.6...

Hi Ivan, On Mar 3, 2012, at 4:48 AM, Ivan Llopard <ivanllopard at gmail.com> wrote: > Hi, > > I'm facing a problem in llvm while porting it to a new target and I'll > need some support. > We have 2 kind of register, one for general purposes (i.e. arithmetic, > comparisons, etc.) and the other for memory addressing. OK. Separate register classes should be able

Hi, I'm facing a problem in llvm while porting it to a new target and I'll need some support. We have 2 kind of register, one for general purposes (i.e. arithmetic, comparisons, etc.) and the other for memory addressing. Cross copies are not allowed (no data path). We use clang 3.0 to produce assembler code. Because both registers have the same size and type (i16), I don't know