Displaying 2 results from an estimated 2 matches for "iselect".
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2015 Jan 19
2
[LLVMdev] Vectorization Cost Models and Multi-Instruction Patterns?
...for the saturation), and a truncate (output); these all fold alway.
With an intrinsic, you'd end up with a better estimate; however, I'm
trying to see what problems we would encounter without intrinsics, and
I think this is the biggest one.
Note that AFAICT, costs for min/max patterns (icmp+iselect) are also
overestimated, but not as much as saturate.
Proposal:
Add a method, part of the vector API of TargetTransformInfo, for
multi-instruction cost computation. It would take a scalar
Instruction, and a reference to a set of Instruction. If it's able to
match a min/max/saturate/.., it...
2017 Jul 24
2
How to lower a 'Store' node using the list<dag> pattern.
...bits<9> RegB;
let Inst{19-11} = RegA;
let Inst{8-0} = RegB;
}
SURegisterOperand are 16 bits operands.
During the generation of ISelection matchers tables, I got the following assertion.
This assertion start to occur when the pattern is introduced on the MOVSUTO_SU_rr.
How to avoid such assertion? What is a concrete type? According to the definition of SURegisterOperand, these are 16 bits signed integer.
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