Displaying 5 results from an estimated 5 matches for "isehpad".
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ideapad
2020 Jun 17
2
InstCombine doesn't delete instructions with token
...e next to last instruction.
Instruction *Inst = &*--EndInst->getIterator();
- if (!Inst->use_empty())
+ if (!Inst->use_empty() && !Inst->getType()->isTokenTy())
Inst->replaceAllUsesWith(UndefValue::get(Inst->getType()));
- if (Inst->isEHPad()) {
+ if (Inst->isEHPad() || Inst->getType()->isTokenTy()) {
EndInst = Inst;
@@ -3022,7 +3022,8 @@ static bool prepareICWorklistFromFunction(Function
&F, const DataLayout &DL,
++NumDeadInst;
MadeIRChange = true;
}
Inst->eraseFromPar...
2020 Jun 17
2
InstCombine doesn't delete instructions with token
...n.
> Instruction *Inst = &*--EndInst->getIterator();
> - if (!Inst->use_empty())
> + if (!Inst->use_empty() && !Inst->getType()->isTokenTy())
> Inst->replaceAllUsesWith(UndefValue::get(Inst->getType()));
> - if (Inst->isEHPad()) {
>
> + if (Inst->isEHPad() || Inst->getType()->isTokenTy()) {
> EndInst = Inst;
> @@ -3022,7 +3022,8 @@ static bool prepareICWorklistFromFunction(Function
> &F, const DataLayout &DL,
> ++NumDeadInst;
> MadeIRChange = true;
&g...
2020 Jun 17
2
InstCombine doesn't delete instructions with token
...n.
> Instruction *Inst = &*--EndInst->getIterator();
> - if (!Inst->use_empty())
> + if (!Inst->use_empty() && !Inst->getType()->isTokenTy())
> Inst->replaceAllUsesWith(UndefValue::get(Inst->getType()));
> - if (Inst->isEHPad()) {
>
> + if (Inst->isEHPad() || Inst->getType()->isTokenTy()) {
> EndInst = Inst;
> @@ -3022,7 +3022,8 @@ static bool prepareICWorklistFromFunction(Function
> &F, const DataLayout &DL,
> ++NumDeadInst;
> MadeIRChange = true;
&g...
2019 Jun 27
3
[cfe-dev] [RFC] ASM Goto With Output Constraints
What about SelectionDAG representation? Currently we expand callbr to
INLINEASM_BR and BR. Both of which are terminators. But in order to support
outputs we would need to put CopyFromReg nodes between them.
~Craig
On Thu, Jun 27, 2019 at 12:18 PM Nick Desaulniers via cfe-dev <
cfe-dev at lists.llvm.org> wrote:
> + CBL mailing list
>
>
> On Thu, Jun 27, 2019 at 11:08 AM Bill
2015 Sep 14
7
RFC: speedups with instruction side-data (ADCE, perhaps others?)
I’ve been playing around with optimizing performance various passes and noticed something about ADCE: it keeps an Alive set that requires a lot of upkeep time-wise, but if each instruction had a /single bit/ of side data (to represent liveness, solely within the pass), the set wouldn’t be needed. I tested this out and observed a ~1/3 reduction in time in ADCE: 1454ms to 982ms according to a