Displaying 5 results from an estimated 5 matches for "isdesirabletopromoteop".
2012 May 23
2
[LLVMdev] Predicate registers/condition codes question
...On 22/05/2012 23:25, Sebastian Pop wrote:
>> So my question is how do we specify that for most of the operations i8
>> should be promoted to i32 and that only a few logical operations are
>> legal on i8?
>
> I think the combo TargetLowerInfo::isTypeDesirableForOp() and
> IsDesirableToPromoteOp() may help you here. X86 does something similar.
I just tried these functions, and it seems like they are only
modifying the behavior of type promotions for a small subset of
operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL, vis...
2012 May 24
0
[LLVMdev] Predicate registers/condition codes question
...bastian Pop wrote:
>>> So my question is how do we specify that for most of the operations i8
>>> should be promoted to i32 and that only a few logical operations are
>>> legal on i8?
>>
>> I think the combo TargetLowerInfo::isTypeDesirableForOp() and
>> IsDesirableToPromoteOp() may help you here. X86 does something similar.
>
> I just tried these functions, and it seems like they are only
> modifying the behavior of type promotions for a small subset of
> operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> PromoteLoad, SimplifyBinOpWithSameOp...
2012 May 22
0
[LLVMdev] Predicate registers/condition codes question
...e
> registers can only be used in a few logical operations.
>
> So my question is how do we specify that for most of the operations i8
> should be promoted to i32 and that only a few logical operations are
> legal on i8?
I think the combo TargetLowerInfo::isTypeDesirableForOp() and
IsDesirableToPromoteOp() may help you here. X86 does something similar.
Ivan
>
> Thanks,
> Sebastian
> --
> Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
>
> PS: I have tried to tweak the TransformToType table to specify the
> type promotion i8 -> i32, by doing the followi...
2012 May 22
2
[LLVMdev] Predicate registers/condition codes question
Hi Eli,
On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote:
>> Hey folks,
>>
>> We are having some difficulty with how we have been representing our
>> predicate registers, and wanted some advice from the list. First, we
>> had been
2012 May 24
3
[LLVMdev] Predicate registers/condition codes question
...t;> So my question is how do we specify that for most of the
> >>> operations i8 should be promoted to i32 and that only a few
> >>> logical operations are legal on i8?
> >>
> >> I think the combo TargetLowerInfo::isTypeDesirableForOp() and
> >> IsDesirableToPromoteOp() may help you here. X86 does something
> >> similar.
> >
> > I just tried these functions, and it seems like they are only
> > modifying the behavior of type promotions for a small subset of
> > operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> &g...