search for: isdef

...rt is in LiveIntervals::getSpillWeight. Do we have to scale the values somehow there? > > Yes, BlockFrequency::getFrequency() is poorly named, it returns a fixpoint number. I think you should scale it to be relative to the entry block frequency. > > +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { > + return (isDef + isUse) * freq.getFrequency(); > } > > This computation can overflow. Yep, I went down the easy route and converted it to floating point arithmetic. Is that OK here? > > @@ -178,9 +180,10 @@ bool SpillPlacement::runOnMach...

...gt; > The bottom word of this MachineOperand now looks like this, with > (according to Valgrind) the x's corresponding to uninitialized bits: > > xxxx xxxx xxxx 0000 0000 0000 0000 0100 > > At this point isReg() can be called safely since it looks only at the > lower bits. isDef() cannot be called safely because it looks at bit 25. > However it is clear that the C++ code (below) never calls isDef() when > isReg() returns false, as it does here. > > So now back to the asm: > > 0000000000000000 > <_Z6xfuncxPKN4llvm14MachineOperandEPKNS_18TargetRegist...

...t this line: https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/DeadMachineInstructionElim.cpp#L142 Here I've refactored the code into a minimal (noinline) function that still triggers the problem. xfunc2() and xfunc3() are also noinline. The problem goes away if either isReg() or isDef() is marked noinline. void xfuncx(const MachineOperand &MO, const TargetRegisterInfo *TRI, BitVector &LivePhysRegs) { if (MO.isReg() && // <<<<------ problem reported here MO.isDef()) { xfunc2(MO, TRI, LivePhysRegs); } else { xfunc3(MO,...

...n Jun 17, 2013, at 10:48 AM, Benjamin Kramer <benny.kra at gmail.com> wrote: > [Splitting this out from the original thread to reduce noise in it] > > > On 17.06.2013, at 18:43, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { >> + return (isDef + isUse) * freq.getFrequency(); >> } >> >> This computation can overflow. > > Yep, I went down the easy route and converted it to floating point arithmetic. Is that OK here? Yes, that should be fine. +LiveInte...

Dear Tim, Thank you for your thorough reply. So, based on your reply I get every operand and check them to be (isDef && !isimplicit). Now my problem is that it gives me the physical register number.i.e, for example, instead of r0, it return %physreg66. Could you please help me on how to convert these physical register number to the ARM related register? I mean the 15 GPRs in ARM. Thank you, Fami On Sat,...

...defusechain_instr_iterator(MachineOperand *op) : Op(op) { // If the first node isn't one we're interested in, advance to one that // we are interested in. if (op) { if ((!ReturnUses && op->isUse()) || - (!ReturnDefs && op->isDef()) || + (!ReturnDefs && op->isDef() && !op->readsReg()) || (SkipDebug && op->isDebug())) advance(); } } friend class MachineRegisterInfo; @@ -907,11 +907,11 @@ public: else assert(!Op...

Hello everyone, I am trying to write a code to do the following: 1. Get an ARM machine instruction 2. Find destination register of that instruction that has been written 3. set a bit in a vector, according to that register number. (Since it's ARM, I have a 15 bit vector) It means if I have : add r0, r1, r0 I want to get r0 as dest reg and set the index 0 of my vector to 1. I get my machine

...ister with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg, false, // isDef true)); // isImplicit As, can be seen, it is presumed that this operand is always the last operand, this is however not the case. It in fact becomes the first of the impl-use operands. It might be preferred to change the addOperand(), so as to always...

...only interesting part is in LiveIntervals::getSpillWeight. Do we have to scale the values somehow there? Yes, BlockFrequency::getFrequency() is poorly named, it returns a fixpoint number. I think you should scale it to be relative to the entry block frequency. +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { + return (isDef + isUse) * freq.getFrequency(); } This computation can overflow. @@ -178,9 +180,10 @@ bool SpillPlacement::runOnMachineFunction(MachineFunction &mf) { // Compute total ingoing and outgoing block frequencies for all bundles. BlockFr...

...register number, only valid for MO_Register. A > value of 0 > + /// indicates the MO_Register has no subReg. > + unsigned char SubReg; > + > + /// TargetFlags - This is a set of target-specific operand flags. > + unsigned char TargetFlags; > + }; > > /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for > MO_Register > /// operands. > @@ -176,9 +179,17 @@ > /// > MachineOperandType getType() const { return > (MachineOperandType)OpKind; } > > - unsigned char getTargetFlags() const { return TargetFlags; } > -...

On 17.06.2013, at 15:56, Diego Novillo <dnovillo at google.com> wrote: > On 2013-06-15 16:39 , Benjamin Kramer wrote: >> Do you want to take over this effort or should I poke more at it? > > Since you've already started, it's easier if you poke more at it. Thanks. I've got a whole bunch of other things to go through. OK, will do. Jakob any comments on the

Dear there, I am trying to use liveness of a variable while writing a machinefunction pass. But it seems that some virtual registers are not marked as dead while they should be (never used by anything else). I get those info by callings isDead or isDef function for that MachineOperand (vreg). Is there a way to get more accurate liveness info? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160728/8bb11df6/attachment.html>

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will find R4 first is killed, then is used. It can not unlogisch. Attually R4 just is <Used>. It will c...

...Register. A >> value of 0 >> + /// indicates the MO_Register has no subReg. >> + unsigned char SubReg; >> + >> + /// TargetFlags - This is a set of target-specific operand flags. >> + unsigned char TargetFlags; >> + }; >> >> /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for >> MO_Register >> /// operands. >> @@ -176,9 +179,17 @@ >> /// >> MachineOperandType getType() const { return >> (MachineOperandType)OpKind; } >> >> - unsigned char getTargetFlags() const...

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same thing. > R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will...

...ister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

Hi Quentin, On 08/15/14 19:01, Quentin Colombet wrote: [...] >> The question is: How should true subregister definitions be >> expressed so that they do not interfere with each other? See the >> detailed problem description below. > > We do have a limitation in our current liveness tracking for > sub-register. Therefore, I am not sure that is possible. > >

Is it possible to get a virtual register and then use that to create a real register? I've seen it done in unittests/CodeGen/MachineInstrTest.cpp like this: unsigned VirtualDef1 = -42; VD1VU->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); But when I do that in my code I get an assertion so I wasn't sure if it's legal or not. Thanks. ________________________________ From: David Greene <dag at cray.com> Sent: Wednesday, January 2, 2019 9:23 AM To: m m Cc: via llvm-dev Subject: Re: [llvm-dev] New to LLVM. Nee...

...:37 PM, Xiaochu Liu via llvm-dev wrote: > > I am trying to use liveness of a variable while writing a > machinefunction pass. But it seems that some virtual registers are not > marked as dead while they should be (never used by anything else). I get > those info by callings isDead or isDef function for that MachineOperand > (vreg). Is there a way to get more accurate liveness info? The absence of these flags does not mean anything, but if they are present, then they must be correct. You can always use functions use_empty and use_nodbg_empty, both in MachineRegisterInfo. A pre...

Hey, guys, could someone tell me some high level things about the version of linear scan that you use? 1) The heuristics for spilling seems to be: (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth besides not spilling defs that are immediatly followed by uses, do you do any other thing, such as, taking into consideration the size of the interval when spilling? 2) How do you avoid conflicts with machine registers already in the target code, such as the on...