Displaying 10 results from an estimated 10 matches for "isdebugvalu".
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isdebugvalue
2012 Apr 10
1
[LLVMdev] Bug in MachineRegisterInfo ?
...odbg_begin(0), re = MRI->use_nodbg_end();
ri != re; ++ri) {
MachineInstr *UseMI = &*ri;
UseMI->dump ();
}
}
*****
But I see that UseMI is
DBG_VALUE %noreg, 0, !"foobar"; line no:511 inlined @[ foo.cc:364:5 ]
Also, when I want to check what "isDebugValue" returns, I get this.
(gdb) p UseMI->isDebugValue()
$1 = true
Isn't this a bug ? There seems to be something wrong or am I missing
something ?
TIA,
Pranav
Qualcomm Innovation Center (QuIC) is a member of the Code Aurora Forum.
2011 Dec 05
0
[LLVMdev] RFC: Machine Instruction Bundle
...mportant that this can be used for more than VLIW targets. Besides the uses you mention, I would like to use bundle DBG_VALUE instructions so we can avoid silly code like this:
MachineBasicBlock::iterator InsertPos = mi;
while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
--InsertPos;
MachineBasicBlock::iterator From = KillMI;
MachineBasicBlock::iterator To = llvm::next(From);
while (llvm::prior(From)->isDebugValue())
--From;
I also think bundles can be used for implementing parallel copies.
Value Semantics
===============
The register allo...
2016 Aug 17
2
CodeView and "line 0" ?
I mean, we just skip over instructions without a DebugLoc:
void CodeViewDebug::beginInstruction(const MachineInstr *MI) {
DebugHandlerBase::beginInstruction(MI);
// Ignore DBG_VALUE locations and function prologue.
if (!Asm || !CurFn || MI->isDebugValue() ||
MI->getFlag(MachineInstr::FrameSetup))
return;
DebugLoc DL = MI->getDebugLoc();
if (DL == PrevInstLoc || !DL)
return;
maybeRecordLocation(DL, Asm->MF);
}
Seems reasonable to extend the condition with ' || DL->getLine() == 0'. I'm
not aware of a goo...
2016 Sep 29
2
[RFC] Interprocedural MIR-level outlining pass
Hi Violeta,
I compiled with
clang -Oz and
clang -Oz -mno-red-zone for comparisons against Oz
and
clang -O0 and
clang -O0 -mno-red-zone for comparisons against a default clang.
I unfortunately don’t have the clang commit I worked with on my home laptop, and don’t have access to the computer I was using at Apple, so I can’t help you there.
Jessica
> On Sep 28, 2016, at 11:22 AM, Violeta
2016 Aug 17
2
CodeView and "line 0" ?
I've been playing with Fred Riss's "line 0" patch for DWARF
(https://reviews.llvm.org/D16569) but in adapting it for current trunk,
I find the DwarfDebug stuff has been refactored to allow either DWARF
or CodeView. That's all good, but the question is whether the "line 0"
patch should be DWARF-specific or common. The DWARF spec explicitly
states that code not
2012 Nov 01
0
[LLVMdev] : Predication on SIMD architectures and LLVM
On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote:
> Hi all,
>
> I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we
2014 Aug 22
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi Quentin,
On 08/19/14 18:58, Quentin Colombet wrote:
[...]
> It seems that you will have to debug further the *** Bad machine code: Instruction loads from dead spill slot *** before we can be of any help.
Yes, I've done some more digging. Sorry for the long mail...
I get:
Inline spilling aN40_0_7:%vreg1954 [5000r,5056r:0)[5056r,5348r:1)
0 at 5000r 1 at 5056r
At this point I have
2012 Oct 31
3
[LLVMdev] : Predication on SIMD architectures and LLVM
Hi all,
I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this
2011 Dec 02
18
[LLVMdev] RFC: Machine Instruction Bundle
Machine Instruction Bundle in LLVM
Hi all,
There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community.
Design Criteria
1. The
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...delete ResourceTracker;
>> -}
>> -
>> -// ignorePseudoInstruction - ignore pseudo instructions.
>> -bool VLIWPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
>> - MachineBasicBlock *MBB) {
>> - if (MI->isDebugValue())
>> - return true;
>> -
>> - if (TII->isSchedulingBoundary(MI, MBB, MF))
>> - return true;
>> -
>> - return false;
>> -}
>> -
>> -// isSoloInstruction - return true if instruction I must end previous
>> -// packet.
>> -...