search for: isdead

...OW<imp-def> ... When constructing a MISched DAG, I expect to see output dependencies (A -> C) and (B -> C). I assert that output dependency (A -> B) is spurious because F_OVERFLOW is dead at B. Indeed, ScheduleDAGInstrs::addPhysRegDeps already includes a test for this case (if MO.isDead()), confirming that the developer intended to omit output dependencies on dead registers. However, the LiveVariables pass clears the isDead flag from all operands that reference F_OVERFLOW and does not reset those flags. Without this information MISched builds the pessimistic graph including the...

Is there anything that documents what these properties (and the other similar properties) do on the MachineOperand class? I’m trying to debug an instruction selection issue I think. It’s hard to find documentation on what the MO properties mean. Thanks, Carl

The isKill must be correct if present, but a vreg may still be killed even if the operand has no Kill flag. The isDead and isUndef flags however are required to be correct. We need further details to say anything about your problem, a LiveIntervals::dump() dump for example would be helpful to assess whether the liveness data is correct in your case. - Matthias > On Jul 28, 2016, at 1:42 PM, Krzysztof Parzyszek...

...s so it’s value is no longer available to later instructions”? > On 11 Mar 2019, at 16:43, Quentin Colombet <qcolombet at apple.com> wrote: > > Hi Carl, > > Look at the comments in include/llvm/CodeGen/MachineOperand.h for the documentation of the various flags. > > IsDead means that a definition is never used. > IsKill means that this is the last use of a given register. > > Cheers, > -Quentin > >> On Mar 11, 2019, at 8:54 AM, LLVM Mailing List via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Is there anything that doc...

On 7/28/2016 3:49 PM, Matthias Braun wrote: > > The isDead and isUndef flags however are required to be correct. Undef yes, but what relies on isDead being accurate (before live interval computation)? -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

> On Jul 28, 2016, at 1:52 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > > On 7/28/2016 3:49 PM, Matthias Braun wrote: >> >> The isDead and isUndef flags however are required to be correct. > > Undef yes, but what relies on isDead being accurate (before live interval computation)? I only remember Andy/Quentin making those conservative correctness claims about the kill flags but not the dead/undef flags. I am also pretty sure...

Dear there, I am trying to use liveness of a variable while writing a machinefunction pass. But it seems that some virtual registers are not marked as dead while they should be (never used by anything else). I get those info by callings isDead or isDef function for that MachineOperand (vreg). Is there a way to get more accurate liveness info? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160728/8bb11df6/attachment.html>

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will find R4 first is killed, then is used. It can not unlogisch. Attually R4 just is <Used>. I...

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same thing. > R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]...

.../28/2016 3:37 PM, Xiaochu Liu via llvm-dev wrote: > > I am trying to use liveness of a variable while writing a > machinefunction pass. But it seems that some virtual registers are not > marked as dead while they should be (never used by anything else). I get > those info by callings isDead or isDef function for that MachineOperand > (vreg). Is there a way to get more accurate liveness info? The absence of these flags does not mean anything, but if they are present, then they must be correct. You can always use functions use_empty and use_nodbg_empty, both in MachineRegisterInf...

...duplicate COPYs are being generated, why? One for each use? The reg_bundle holds these multiple copies so that we are iterating over the same exact COPY instructions multiple times, even though each one hits the same spot in the function: if (hoistSpill(OldLI, MI)) { MI->getOperand(0).setIsDead(); DeadDefs.push_back(MI); continue; } Even when I add a check: if (MI->getOperand(0)->isDead()) continue; This never checks to true, on the second, third, fourth, etc duplicate. Not sure what I'm missing? Can someone give me a brief description of why these multiple COP...

Hi Andrew, While working on the MSP430 backend, I noticed code that compiled fine before hitting an assert which you have recently inserted in r184574. More specifically, in InlineSpiller.cpp:1076 the following assert is triggered: > assert(MO->isDead() && "Cannot fold physreg def"); I wouldn't be surprised is the underlying cause is in the MSP430 backend but I wanted to consult you before diving into the code. Is this assert really necessary? If I change to code to simply "continue" on "!MO->isDead()&...

...l 28, 2016, at 2:01 PM, Matthias Braun via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > >> On Jul 28, 2016, at 1:52 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: >> >> On 7/28/2016 3:49 PM, Matthias Braun wrote: >>> >>> The isDead and isUndef flags however are required to be correct. >> >> Undef yes, but what relies on isDead being accurate (before live interval computation)? > I only remember Andy/Quentin making those conservative correctness claims about the kill flags but not the dead/undef flags. I am als...

...for (const auto &OpPair : Ops) { MachineOperand &MO = OpPair.first->getOperand(OpPair.second); MO.setReg(NewVReg); if (MO.isUse()) { if (!OpPair.first->isRegTiedToDefOperand(OpPair.second)) MO.setIsKill(); } else { if (!MO.isDead()) hasLiveDef = true; } So I suppose we could either make LiveIntervals::computeDeadValues mark the individual defs dead as well, or we could change InlineSpiller::spillAroundUses so that if we only look at the BUNDLE instruction (if it exists) in case of bundled instructions...

...sDef flag is implied by the use of the register before the '=', unless it's implicit. - TiedTo and IsEarlyClobber aren't not serialized, as they are defined by the instruction description. (I believe that's true in all cases, but I'm not 100% sure). - IsUndef, IsImp, IsKill, IsDead, IsInternalRead, IsDebug - keywords like 'implicit', 'undef', 'kill', 'dead' are used before the register e.g. 'undef %rax', 'implicit-def kill %eflags'. I don't have a syntax for the SubReg_TargetFlags at the moment. Alex > > - .....

...not appropriate. Cheers, -Quentin > > The reg_bundle holds these multiple copies so that we are iterating over the same exact COPY instructions multiple times, even though each one hits the same spot in the function: > > if (hoistSpill(OldLI, MI)) { > MI->getOperand(0).setIsDead(); > DeadDefs.push_back(MI); > continue; > } > > Even when I add a check: > > if (MI->getOperand(0)->isDead()) > continue; > > This never checks to true, on the second, third, fourth, etc duplicate. > > Not sure what I'm missing? Can s...

...s to truly mean Reg or a super-register of Reg is defined, not any overlapping Reg is defined. The code looks like this: bool IsRegOrSuperReg = MOReg == Reg || TRI->isSuperRegister(MOReg, Reg); ... if (IsRegOrSuperReg) { PRI.Defines = true; // Reg or a super-register is defined. if (!MO.isDead()) AllDefsDead = false; } I think the fundamental bug here is that the operands are swapped when passed into isSuperRegister. The definition of isSuperRegister is /// \brief Returns true if RegB is a super-register of RegA. bool isSuperRegister(unsigned RegA, unsigned RegB) const; so, it lo...

On using builtin functions we have to move the input to registers $0 and $1, if one of the input value is an immediate, we fail to propagate the immediate: ... mov u32 $r477 0x00000003 (0) ... mov u32 $r0 %r473 (0) mov u32 $r1 $r477 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... With this patch the immediate is propagated, potentially causing the first MOV to be superfluous, which we'd

...FILE_IMMEDIATE)) + bld.mkMovToReg(s, i->getSrc(s)); + else { + bld.mkMovToReg(s, ld->getSrc(0)); + // Clear the src, to make code elimination possible here before we + // delete the instruction i later + i->setSrc(s, NULL); + if (ld->isDead()) + delete_Instruction(prog, ld); + } + } + switch (i->dType) { case TYPE_U32: builtin = NVC0_BUILTIN_DIV_U32; break; case TYPE_S32: builtin = NVC0_BUILTIN_DIV_S32; break; -- 2.14.0

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;