search for: iscall

...n epilogue in the final emitted code, and insert a NOP between them if that happens. My initial attempt at it looked like this: MachineBasicBlock& MBB; MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would be inserted if (MBBI != MBB.begin() ? MBBI->getPrevNode()->isCall() : MBB.getPrevNode()->back().isCall()) { // insert NOP } However, this did not work because at the stage where I am trying to do this (in X86FrameLowering::emitEpilogue), the MBBs look like this: BB0: ... CALL ... <-- call I am trying to detect EH_LABEL ... <--| the...

I cannot understand the following error printed out when I try to get the extrema of my time series. I would appreciate some suggestion as I really cannot interpret the error. I might not be using a proper set of parameters in calling such functions. I am learning by doing ... > aa.peak <- wavCWTPeaks (aa.tree) Error in `row.names<-.data.frame`(`*tmp*`, value = c("1",

...at I should not remove are the calls. Is it true? I would like to know if a code like this below is safe, that is, besides call instructions, is there other instructions that must stay in the code even if their definitions are dead? MachineInstr * mi = iter; opCode = // get the opcode of mi if(!mi.isCall(opCode)) { mbb.remove(iter); } Thank you, Fernando

...ix below resolves the issue, but may be too big of a hammer? @@ -802,17 +836,8 @@ void CachingMemorySSAWalker::invalidateInfo(MemoryAccess *MA) { doCacheRemove(MA, Q, Q.StartingLoc); return; } - // If it is not a use, the best we can do right now is destroy the cache. - bool IsCall = false; - - if (auto *MUD = dyn_cast<MemoryUseOrDef>(MA)) { - Instruction *I = MUD->getMemoryInst(); - IsCall = bool(ImmutableCallSite(I)); - } - if (IsCall) - CachedUpwardsClobberingCall.clear(); - else - CachedUpwardsClobberingAccess.clear(); + CachedUpwardsCl...

...m/DisassemblerLLVMC.cpp:87 - "const bool can_branch = mc_disasm_ptr->CanBranch(inst);"), while trying to set the next breakpoint. On this case, the instruction is the "bne cr7,0x2000092c", which is a branch, but at llvm/lib/MC/MCInstrDesc.cpp:35 - "if (isBranch() || isCall() || isReturn() || isIndirectBranch())" it returns false, making lldb do not set the correct breakpoint, so the execution does not stop at next line, which should be the "step over" behavior. The variable "Flags" for the disassembled instruction does not have the branch fl...

Hi, Recently, I am working on some information collection on the machine instruction (MachineInstr) level. But, sometimes, I need check the corresponding IR level instruction of the a machine instruction. When visiting a machine instruction which is a call (MachineInstr::isCall()), I need to check the arguments of this call site. I know that the CallSite class provides good facility for this work, but the CallSite can be constructed only fromInstruction rather than MachineInstr. Is there any workaround? Thanks. -- Best regards, Li Qingan -------------- next part ----...

...ass and it's causing a miscompilation by hoisting a divide by zero instruction out of the loop. Clearly this pass needs to be made aware that this is not safe. The current test in the MachineLICM is as follows: // Ignore stuff that we obviously can't hoist. if (TID.mayStore() || TID.isCall() || TID.isReturn() || TID.isBranch() || TID.hasUnmodeledSideEffects()) return false; Setting hasSideEffects = 1 seems to work, but I'm not sure if that's the intended use of this flag. I notice that divide / remainder instructions for other architectures are not marked in this...

...on which the kernel handles itself. Details here: http://gcc.gnu.org/ml/gcc-patches/2008-07/msg00025.html In order to extend the implementation within LLVM I read the respective documentation. After taking a longer look at how its done for x86 and ARMInstrInfo.td I came up with the following: let isCall = 1, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def ARM_KERNEL_CMPXCHG : ABXI<0b1011, (outs), (ins i32:$oldval, i32:$newval, addr:$dst), "bl 0xffff0fc0", [(ATOMIC_CMP_SWAP addr:$dst, i32:$oldval, i32:$newval)]...

...restored, but then the stack pointer is overwritten with an incorrect value. I've "fixed" this by modifying `ShrinkWrap::useOrDefCSROrFI` to explicitly check for the stack pointer register (using `TLI.getStackPointerRegisterToSaveRestore`) and also to ignore tall call instructions (`isCall() && isReturn()`), since they implictly use SP (for AArch{32,64} at least). Does this look correct? Are there alternatives? Shouldn't `ShrinkWrap::useOrDefCSROrFI` also check whether or not `MachineInstr::Frame{Setup,Destroy}` flags are set? In that case, I suppose an alternative slu...

...number of call-like instructions. We would need copies of CALL*, TCRETURN*, and TAILJMP* for each calling convention. I was hoping we could avoid that, and even get rid of the WINCALL instructions. What if InstrEmitter::EmitMachineNode called a target hook to add call-clobbered registers when II.isCall()? We would need some way of communicating the calling convention to the target hook. An immediate operand could work. /jakob

On Fri, 12 May 2006, Ralph Corderoy wrote: >> If you don't *know* that all (e.g.) function pointers to this code are >> dead (which means that execution could come back to the function), you >> should use the ExecutionEngine::recompileAndRelinkFunction(F) method. > > recompileAndRelinkFunction() overwrites the old machine code with a > branch to the new. Is it

...ug: please > report it! No, EmitBranchToAt() always emits 16 bytes. AtI[0] = BUILD_LIS(12, Addr >> 16); // lis r12, hi16(address) AtI[1] = BUILD_ORI(12, 12, Addr); // ori r12, r12, low16(address) AtI[2] = BUILD_MTCTR(12); // mtctr r12 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl but I understand now how startFunctionStub() is given StubSize and on PowerPC it's 16 so there's no problem. Cheers, Ralph.

...rent ways (e.g. into a noop if fp-eliminating, or into [e.g.] "sub ESP, 40" if not). I think it's a good idea for your target to do similar things, for consistency if nothing else, but if you really want to, I wouldn't be opposed to making that also check for instructions that isCall. -Chris -- http://nondot.org/sabre/ http://llvm.cs.uiuc.edu/

Dear all, I'm facing a problem in estimation of glm model with weibull distribution. I run this : eqn0<-formula(fdh~cup1+cup2+cup3+cup4+fin1+vd1+cm2+cm4+milieu+cpro1+cpro2+cpro3a+cpro3b+schef+log(y)) regWeib0<-vglm(eqn0,family=weibull,subset(br, fdh<1)) I have en estimation but there is a message saying that regularity conditions are violated : Message d'avis : In eval(expr,

...ls. Is it true? > I would like to know if a code like this below is safe, that is, besides > call instructions, is there other instructions that must stay in the code > even if their definitions are dead? > > MachineInstr * mi = iter; > opCode = // get the opcode of mi > if(!mi.isCall(opCode)) { > mbb.remove(iter); > } You can't do that unless you can prove the instructions don't have side effects, which you can't. Higher-level passes will remove dead code. Are you seeing a case where dead code is making it down to the codegen level? -Chris -- http:/...

...; error. LLC > generates code successfully with other standard register allocators > available. I haven't investigated the Sparc backend specifically but... My guess is this is related to this entry in SparcInstrInfo.td: let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1, Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { def CALL : InstSP<(outs), (ins calltarget:$dst), "call $dst", []> { bits<30> di...

...ll > they mark LR used in the function with MRI->addPhysRegsUsed(UsedInInstr); > and LR is callee saved correctly during prolog/epilog insertion. > > But with fast register allocator the following lines ignore the Def on > LR in the call instruction: (line 747) > > if (TID.isCall()) { > // Spill all virtregs before a call. This serves two purposes: 1. If an > // exception is thrown, the landing pad is going to expect to find registers > // in their spill slots, and 2. we don't have to wade through all the > // <imp-def> operands on the call instruction...

On Oct 19, 2010, at 8:00 PM, Jakob Stoklund Olesen wrote: > > > One problem is that calling conventions are handled while building the selection DAG, and the DAG doesn't really know to represent clobbered registers. > > Perhaps X86TargetLowering::LowerCall() could decorate the X86ISD::CALL node with the calling convention somehow? > > Dan, do you have any thoughts on

Hi All, I'm looking into converting LICM to use MemorySSA instead of AliasSets to determine when it is safe to hoist/sink/promote loads and stores to get around the issue of alias set collapse (see discussion [1]). I have a prototype implementation, but have run into two issues that I could use input from the designers of MemorySSA to resolve: 1) Is MemorySSA intended to be

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }