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Hi All, For various obscure reasons I'd like to detect the condition when X86 CALL instruction immediately precedes a function epilogue in the final emitted code, and insert a NOP between them if that happens. My initial attempt at it looked like this: MachineBasicBlock& MBB; MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would be inserted if (MBBI != MBB.begin()

...see attached plot) aats <- ts (aa, deltat =1/30, start = 0.0) aa.cwt <- wavCWT(aats) aa.tree <- wavCWTTree (aa.cwt) I can get the data for each of the 3 branches: > aa.tree[[1]] $itime [1] 135 135 134 133 132 130 128 126 123 122 122 122 122 123 126 $iscale [1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $time [1] 4.466667 4.466667 4.433333 4.400000 4.366667 4.300000 4.233333 4.166667 [9] 4.066667 4.033333 4.033333 4.033333 4.033333 4.066667 4.166667 $scale [1] 0.03333333 0.06666667 0.10000000 0.13333333 0.16666667 0.20000000 [7] 0.23333333 0....

Dear guys, I am working in a register allocator for LLVM, and I realized that, after I perform register allocation, there is many move instructions that are dead code, and can safely be removed. It is easy for the RA algorithm to remove these instructions. It seems to me that the only instructions with dead definitions that I should not remove are the calls. Is it true? I would like to know

Hi Daniel, Thanks for the info. I’ve started looking into converting EarlyCSE to use MemorySSA first since 1) I don’t think it needs any additional MemorySSA update API and 2) the particular case I’m looking at needs EarlyCSE to catch more load cases before LICM to be profitable. I have a prototype working, but have run into two issues: 1) readonly calls are treated as clobbers by

Hi all, I'm working on lldb to make it available to ppc64le, but the "step over" is not working for some cases. When debugging, I can see that the disassembler analyze some instructions forward, looking for a branch instruction (llvm/tools/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp:87 - "const bool can_branch = mc_disasm_ptr->CanBranch(inst);"), while

Hi, Recently, I am working on some information collection on the machine instruction (MachineInstr) level. But, sometimes, I need check the corresponding IR level instruction of the a machine instruction. When visiting a machine instruction which is a call (MachineInstr::isCall()), I need to check the arguments of this call site. I know that the CallSite class provides good facility for this

What are the correct target description side effect flags for instructions which may trap (e.g. divide / remainder)? The divide instruction in my backend currently has no flags set. I've enabled the MachineLICM pass and it's causing a miscompilation by hoisting a divide by zero instruction out of the loop. Clearly this pass needs to be made aware that this is not safe. The current

Hi, I am missing atomic operations support for the ARM backend (see PR #3887) and started trying to implement them. Since this is the first time that I work on such stuff (and llvm) I am going to take the supposedly easy route and provide an implementation that will work on Linux systems. This involves calling a special function which the kernel handles itself. Details here:

Hello, So, I have this testcase: void f(int n, int x[]) { if (n < 0) return; int a[n]; for (int i = 0; i < n; i++) a[i] = x[n - i - 1]; for (int i = 0; i < n; i++) x[i] = a[i] + 1; } that, compiled with -O1/-Os for AArch64 and X86, generates machine code, which fails to properly restore the stack pointer upon function return.

On Oct 20, 2010, at 11:53 AM, Dan Gohman wrote: > > On Oct 19, 2010, at 8:00 PM, Jakob Stoklund Olesen wrote: >> >> >> One problem is that calling conventions are handled while building the selection DAG, and the DAG doesn't really know to represent clobbered registers. >> >> Perhaps X86TargetLowering::LowerCall() could decorate the X86ISD::CALL node

On Fri, 12 May 2006, Ralph Corderoy wrote: >> If you don't *know* that all (e.g.) function pointers to this code are >> dead (which means that execution could come back to the function), you >> should use the ExecutionEngine::recompileAndRelinkFunction(F) method. > > recompileAndRelinkFunction() overwrites the old machine code with a > branch to the new. Is it

Hi Chris, > On Fri, 12 May 2006, Ralph Corderoy wrote: > > recompileAndRelinkFunction() overwrites the old machine code with a > > branch to the new. Is it always guaranteed that there's space to > > write the new branch instructions? > > Yes. OK. > > A quick look suggests the x86 takes five bytes, PowerPC 16, > > PPC should be 4 bytes in the normal

yOn Wed, 23 Mar 2005, Vladimir Prus wrote: >> How is your target different here? Can you give an example of why this >> causes a problem? > > Here's the code which computes the hasCalls flag: > > bool HasCalls = false; > > for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) > for (MachineBasicBlock::iterator I = BB->begin(); I

...n<-length(x) ????? a<-p[1] ????? b<-p[2] ????? t1<-(mu-b*gamma(1+1/a))^2 ????? t2<-(sig-((b^2)*gamma(1+2/a)-mu^2))^2 ????? rval<-t1+t2 ????? rval ? } ? optim(c(1,1),f)$par } With the founded initial values I have I have the message. But When try great initial value for ishape and iscale I have this regWeib0<-vglm(eqn0,family=weibull(lshape='logoff',lscale='loge',eshape=list(offset=-2),ishape=22,iscale=6),subset(br, fdh<1)) Messages d'avis : 1: In checkwz(wz, M = M, trace = trace, wzeps = control$wzepsilon) : ? 1525 elements replaced by 1.819e-12 2: In...

On Thu, 29 Jun 2006, Fernando Magno Quintao Pereira wrote: > I am working in a register allocator for LLVM, and I realized that, > after I perform register allocation, there is many move instructions that > are dead code, and can safely be removed. It is easy for the RA algorithm > to remove these instructions. It seems to me that the only instructions > with dead definitions

On Jan 7, 2011, at 2:36 PM, Venkatraman Govindaraju wrote: > When I run LLC with option "-O0 -march=sparc" on following testcase, > fast register allocator crashes with "UNREACHABLE executed" error. LLC > generates code successfully with other standard register allocators > available. I haven't investigated the Sparc backend specifically but... My guess is

On Jun 4, 2010, at 3:05 AM, Sylvere Teissier wrote: > > In my target the CALL instruction change the link Register %LR > In the target InstrInfo.td I have "Defs=[LR]" on the CALL instruction > definition to handle that. So your CALL instructions are clobbering your callee-saved registers, eh? ;-) > It works well with others registers allocators: when there is a call

On Oct 19, 2010, at 8:00 PM, Jakob Stoklund Olesen wrote: > > > One problem is that calling conventions are handled while building the selection DAG, and the DAG doesn't really know to represent clobbered registers. > > Perhaps X86TargetLowering::LowerCall() could decorate the X86ISD::CALL node with the calling convention somehow? > > Dan, do you have any thoughts on

Hi All, I'm looking into converting LICM to use MemorySSA instead of AliasSets to determine when it is safe to hoist/sink/promote loads and stores to get around the issue of alias set collapse (see discussion [1]). I have a prototype implementation, but have run into two issues that I could use input from the designers of MemorySSA to resolve: 1) Is MemorySSA intended to be

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }