search for: isbundl

> On Jun 28, 2017, at 5:10 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Oh wait, vreg1 is indeed used. > Yeah, having a dead flag here sounds wrong. I mean on the instruction itself. On the bundle, that’s debatable. That would fit the semantic “if no side effect you can kill it” (here there is side effect, we define other vregs). > >> On

Hi Quentin and llvm-dev, I've got a regalloc-related question that you might have an opinion or answer about. In our out-of-tree target we've been doing some bundling before register allocation for quite some time now, and last night a new problem popped up. What the fix should be depends on if this bundle is legal or not: BUNDLE %vreg39<imp-def,dead> *

Hello, I am working on backend development and would like to utilize my target's MCAsmParser inside of an MCInst-level class implementation. I noticed that the AsmParser is registered with the target registry however I am having no luck grepping for a "template" of how to instantiate it and have yet to find specific documentation on how it is done. Any ideas or help is greatly

...--- lib/CodeGen/TailDuplication.cpp (revision 211103) +++ lib/CodeGen/TailDuplication.cpp (working copy) @@ -453,6 +453,11 @@ } } PredBB->insert(PredBB->instr_end(), NewMI); + + /// If there is bundled instruction in TailBB, + /// make bundled instruction in PredBB. + if (MI->isBundled() && MI->isInsideBundle()) + NewMI->bundleWithPred(); } /// UpdateSuccessorsPHIs - After FromBB is tail duplicated into its predecessor

On Thu, Mar 29, 2012 at 03:51:10PM -0700, Andrew Trick wrote: > > On Mar 29, 2012, at 1:18 PM, Tom Stellard <thomas.stellard at amd.com> wrote: > > > On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: > >> Tom, > >> > >> I do not have your call stack, but packetizer calls > >> ScheduleDAGInstrs::buildSchedGraph to create

...chineInstr *MI, >> /// the current output stream. >> /// >> void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { >> - MCInst MCI; >> - >> - HexagonLowerToMC(MI, MCI, *this); >> - OutStreamer.EmitInstruction(MCI); >> + if (MI->isBundle()) { >> + std::vector<const MachineInstr*> BundleMIs; >> + >> + const MachineBasicBlock *MBB = MI->getParent(); >> + MachineBasicBlock::const_instr_iterator MII = MI; >> + ++MII; >> + unsigned int IgnoreCount = 0; >> + while (MI...