Displaying 5 results from an estimated 5 matches for "isbitset".
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isbitseta
2015 Jan 30
0
[LLVMdev] IR extension proposal: bitset constants
...cs and will only work with LTO and not native linkers is also really weird to me. Is there other precedent for that? The only cases I know that affect LTO add information that is safe to drop (e.g. TBAA etc).
Also, your patch is incomplete. Presumably you have to scatter checks for “if (!GV->isBitSet())” throughout the optimizer, codegen and other things that touch globals.
-Chris
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2015 Jan 30
3
[LLVMdev] IR extension proposal: bitset constants
On Thu, Jan 29, 2015 at 02:22:48PM -0800, Peter Collingbourne wrote:
> I've been working on a patch that implements the bitset attribute and bitset
> lowering pass. I'll see if I can send it out later today.
http://reviews.llvm.org/D7288
Thanks,
--
Peter
2009 Jan 26
1
ups emerson liebert GTX2 ESP-II serial protocol demo
..../upsesp2 /dev/ttyS0 Replace ttyS0 with your serial port (ttyS1, ...etc).
*/
#define BAUDRATE B2400
#define _POSIX_SOURCE 1 /* POSIX compliant source */
#define FALSE 0
#define TRUE 1
#define NCMD 100 /*max number of commands*/
#define MAXAGE 5 /*max seconds to accept data as current*/
#define IsBitSet(val, bit) ((val) & (1 << (bit)))
char str[128];
/***************************************************/
typedef struct
{
char descr[120];
unsigned char type; /*0:measurement, 1:ascii, 2:status*/
unsigned char length; /*for ascii, how many cmds*/
unsigned char rfmt; /*unit divi...
2015 Jan 30
2
[LLVMdev] IR extension proposal: bitset constants
...r wrote:
> I don’t think that adding an IR construct for this is the way to go. You’re making IR complicated for everyone to serve a very narrow use case (one that admittedly I don’t really understand).
> Also, your patch is incomplete. Presumably you have to scatter checks for “if (!GV->isBitSet())” throughout the optimizer, codegen and other things that touch globals.
I'll address these points simultaneously because I would like to explain
why extensive support for the new construct is not required, and why the
maintenance burden is not as large as it might seem (and why my patch doe...
2015 Sep 14
7
RFC: speedups with instruction side-data (ADCE, perhaps others?)
I’ve been playing around with optimizing performance various passes and noticed something about ADCE: it keeps an Alive set that requires a lot of upkeep time-wise, but if each instruction had a /single bit/ of side data (to represent liveness, solely within the pass), the set wouldn’t be needed. I tested this out and observed a ~1/3 reduction in time in ADCE: 1454ms to 982ms according to a