search for: isbeforelegalizeops

Displaying 6 results from an estimated 6 matches for "isbeforelegalizeops".

2019 Aug 26
2
LLVM X86 backend combineIncDecVector's transform
...on, Aug 26, 2019 at 8:56 PM Topper, Craig <craig.topper at intel.com> > wrote: > > > > I think DAGToDAG is too late because the build_vector has already been > turned into a constant pool load by then so it’s a little difficult to get > back. Maybe we can delay it to !DCI.isBeforeLegalizeOps()? That would at > least let the first DAG combine and the post type legalization DAG combine > see the add, 1. > > > > > > > > +Sanjay as well > > > > > > > > From: Amaury Séchet <deadalnix at gmail.com> > > Sent: Monday, August 26,...
2019 Aug 26
1
LLVM X86 backend combineIncDecVector's transform
I think DAGToDAG is too late because the build_vector has already been turned into a constant pool load by then so it’s a little difficult to get back. Maybe we can delay it to !DCI.isBeforeLegalizeOps()? That would at least let the first DAG combine and the post type legalization DAG combine see the add, 1. +Sanjay as well From: Amaury Séchet <deadalnix at gmail.com> Sent: Monday, August 26, 2019 10:48 AM To: Topper, Craig <craig.topper at intel.com>; llvm-dev at redking.me.uk; efr...
2019 Aug 26
2
LLVM X86 backend combineIncDecVector's transform
Hi all, As you knwo already, I'm trying to change DAGCombiner so that it process the nodes in topological order. Doing so is not difficult per se, but this creates various improvements and regression to the existing test suite. I'd like to work through as many of the regressions as possible ahead of time. One source of such regressions is combineIncDecVector in the X86 backend. It
2012 Feb 07
0
[LLVMdev] DAG optimization and lowering algorithm
On Tue, Feb 7, 2012 at 12:38 AM, Demikhovsky, Elena <elena.demikhovsky at intel.com> wrote: > At the beginning, I have the following chain: LOAD -> TRUNCATE -> ZERO_EXTEND. > After Combine(BeforeLegalizeTypes) the optimization of ZERO_EXTEND  gives me the new chain LOAD -> ANY_EXTEND -> AND. > > I want to optimize ANY_EXTEND but is not analyzed in the same Combine().
2012 Feb 07
2
[LLVMdev] DAG optimization and lowering algorithm
At the beginning, I have the following chain: LOAD -> TRUNCATE -> ZERO_EXTEND. After Combine(BeforeLegalizeTypes) the optimization of ZERO_EXTEND gives me the new chain LOAD -> ANY_EXTEND -> AND. I want to optimize ANY_EXTEND but is not analyzed in the same Combine(). Combine(AfterLegalizeTypes) is no called at all. - Elena -----Original Message----- From: Eli Friedman
2012 Oct 10
2
[LLVMdev] Solicit code review (change to CodeGen)
...ve from a register needs + // only one instruction. + // + // CAVEAT: By replacing a constant with a symbolic value, it may obscure + // some instruction-combining opportunities. This opt needs to be + // postponed as late as possible. + // + if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { + // the DCI.xxxx conditions are provided to postpone the optimization as + // late as possible. + + ConstantSDNode *CmpAgainst = 0; + if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) && + (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.ge...