search for: isasmparseronly

...in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have seen that in Target.td file in class instruction there is a flag isAsmParserOnly which could be used to mark these macros: // Is this instruction a pseudo instruction for use by the assembler parser. bit isAsmParserOnly = 0; but, as far as I can tell, this flag is not available to the AsmParser nor it can be accessed via MCInstrDesc class that we import as externally defin...

...in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have seen that in Target.td file in class instruction there is a flag isAsmParserOnly which could be used to mark these macros: > // Is this instruction a pseudo instruction for use by the assembler parser. > bit isAsmParserOnly = 0; > > but, as far as I can tell, this flag is not available to the AsmParser nor it can be accessed via MCInstrDesc class that we import...

...to call dedicated methods, like dedicated parsers for AsmOperands. Regards Vladimir ________________________________ From: Jim Grosbach [grosbach at apple.com] Sent: Wednesday, October 02, 2013 4:46 AM To: Vladimir Medic Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction Hi Vladimir, ARM does similar things for complex assembly pseudos. Have a look at the definition and use of AsmPseudoInst in the ARM backend. They’re not typically expanding to multiple “real” instructions, but that’s an implementation detail, not a constraint. -Jim O...

...1 src. I am not so familiar with .td format yet, but after some investigation I found it seems impossible to share .td definition of vcvtsi2sd for asm parser and isel. I got success by defining separate .td definition for VCVTSI2SD to fix bug PR9473: define new definition of VCVTSI2SD for isel in isAsmParserOnly = 0 block and move existing VCVTSI2SD definition from isAsmParserOnly = 0 into isAsmParserOnly = 1 block so that existing VCVTSI2SD definition takes effect only in asm parser. Example solution is as follows. lib/Target/X86/x86InstrSSE.td ... multiclass sse12_vcvt_avx_s<bits<8> opc, Reg...

...1, x86memop:$src2, CC:$cc), asm, > [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], > itins.rm, d>, > Sched<[WriteFAddLd, ReadAfterLd]>; > > // Accept explicit immediate argument form instead of comparison code. > let isAsmParserOnly = 1, hasSideEffects = 0 in { > def rri_alt : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), > asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>; > def rmi_alt : PIi8<0xC2, MRMSrcMem, > (outs...

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $