search for: is_affin

Displaying 4 results from an estimated 4 matches for "is_affin".

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2011 Nov 14
1
[LLVMdev] How to make Polly ignore some non-affine memory accesses
...cessing the memory. > --- ./include/polly/TempScopInfo.h 2011-11-13 02:37:59.000000000 +0100 > +++ ../llvm2/tools/polly/./include/polly/TempScopInfo.h 2011-11-13 02:34:47.000000000 +0100 > @@ -45,12 +45,13 @@ > private: > unsigned ElemBytes; > TypeKind Type; > + bool is_affine; I think IsAffine matches more the LLVM coding conventions. > > public: > explicit IRAccess (TypeKind Type, const Value *BaseAddress, > - const SCEV *Offset, unsigned elemBytes) > + const SCEV *Offset, unsigned elemBytes, bool affine)...
2011 Nov 14
0
[LLVMdev] How to make Polly ignore some non-affine memory accesses
.../TempScopInfo.h      2011-11-13 02:37:59.000000000 >> +0100 >> +++ ../llvm2/tools/polly/./include/polly/TempScopInfo.h 2011-11-13 >> 02:34:47.000000000 +0100 >> @@ -45,12 +45,13 @@ >>  private: >>    unsigned ElemBytes; >>    TypeKind Type; >> +  bool is_affine; > > I think IsAffine matches more the LLVM coding conventions. > >> >>  public: >>    explicit IRAccess (TypeKind Type, const Value *BaseAddress, >> -                     const SCEV *Offset, unsigned elemBytes) >> +                     const SCEV *Offset, un...
2011 Nov 02
5
[LLVMdev] How to make Polly ignore some non-affine memory accesses
Mmm I found out a very strange behavior (to me) of the SCEV analysis of the loop bound of the external loop I posted. When in ScopDetection it gets the SCEV of the external loop bound in the "isValidLoop()" function with: const SCEV *LoopCount = SE->getBackedgeTakenCount(L); It returns a SCEVCouldNotCompute, but if I change the "if" block inside the loop from: if
2012 Dec 15
0
[ANNOUNCE] xf86-video-intel 2.20.16
...BLT overwrite detection to use target_handle sna/gen2: Align surface sizes to an even tile sna/gen2: Program solid mask using the DIFFUSE component sna/gen3: Remove incorrect optimisation of an opaque source for CA sna/gen2: Assertions sna/gen2: Initialise channel->is_affine for solid sna/gen2: Reorder reuse_source() to avoid NULL dereference for solids sna/gen3: Remove stray setting of vertex_start sna/gen3: Don't combine primitives if beginning a ca 2-pass sna/gen2+: Experiment with not forcing migration to GPU after CPU rasterisation...