search for: is64bit

...CustomDAGSchedInserter = 1 in { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > + .addReg(ptrA).addReg(ptrB); > + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > + .addReg(incr).addReg(dest); > + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > + .addReg(PPC::R0).addReg(pt...

..._source.html case CallingConv::Intel_OCL_BI <http://llvm.org/docs/doxygen/html/namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974ad47327c131a0990283111588b89587cb>: { if (IsWin64 && HasAVX512) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask; if (Is64Bit && HasAVX512) return CSR_64_Intel_OCL_BI_AVX512_RegMask; if (IsWin64 && HasAVX) return CSR_Win64_Intel_OCL_BI_AVX_RegMask; if (Is64Bit && HasAVX) return CSR_64_Intel_OCL_BI_AVX_RegMask; if (!HasAVX && !IsWin64 &&amp...

...the GHC calling conv intended to be target specific? If it is x86 specific, it should get an X86 prefix. If not, it should move up to be #10 after Cold. 2) In either case, please document the new calling convention in docs/LangRef.html#callingconv 3) IN X86RegisterInfo.cpp, this patch: if (Is64Bit) { if (IsWin64) - return CalleeSavedRegsWin64; + return (ghcCall ? GhcCalleeSavedRegsWin64 : CalleeSavedRegsWin64); else - return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit); + if (ghcCall) + return (callsEHReturn ? + GhcCall...

...ust x86 and SPARC at the moment. At the moment I've just done X86, will try to work on getting it implemented on SPARC next. > 2) In either case, please document the new calling convention in docs/LangRef.html#callingconv Done. > 3) IN X86RegisterInfo.cpp, this patch: > > if (Is64Bit) { > if (IsWin64) > - return CalleeSavedRegsWin64; > + return (ghcCall ? GhcCalleeSavedRegsWin64 : CalleeSavedRegsWin64); > else > - return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit); > + if (ghcCall) > + return (calls...

...patch according to your suggestion.  And I have read > binutil/objdump source code and found that it has a logic that if there's no > symtab, it will use dynsym, which is missing in llvm-objdump. > > Songmao > @@ -747,12 +747,28 @@ error_code ELFObjectFile<target_endianness, is64Bits> template<support::endianness target_endianness, bool is64Bits> error_code ELFObjectFile<target_endianness, is64Bits> ::sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb,...

...n { >> + let Uses = [CR0] in { >> + let Uses = [R0] in >> + def ATOMIC_LOAD_ADD_I32 : Pseudo< >> >> The "let Uses = [R0]" is not needed. The pseudo instruction will be >> expanded like this later: >> >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) >> + .addReg(ptrA).addReg(ptrB); >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) >> + .addReg(incr).addReg(dest); >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) >> + .addRe...

Michael, I have rework the patch according to your suggestion. And I have read binutil/objdump source code and found that it has a logic that if there's no symtab, it will use dynsym, which is missing in llvm-objdump. Songmao -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Fix-the-address-calculation-for-llvm-objdump.patch Type: text/x-patch

Hi all, As previously mentioned on this list the Haskell compiler GHC has a new LLVM based back-end. The back-end needs a new calling convention to efficiently use LLVM and that is what this patch does, just for X86 at the moment. Breakdown: 1) Need actual calling convention Touches: - include/llvm/CallingConv.h - lib/Target/X86/X86CallingConv.td 2) Handling new calling

In a package test I have a problem that needs over 4G of memory. This requires that I use R compiled as a 64 bit application. Is there a way within R to test if R has been compile as a 64 bit application? This would allow me to automatically skip the test when I know it is going to fail. Thanks, Paul Gilbert

In a package test I have a problem that needs over 4G of memory. This requires that I use R compiled as a 64 bit application. Is there a way within R to test if R has been compile as a 64 bit application? This would allow me to automatically skip the test when I know it is going to fail. Thanks, Paul Gilbert

...t. But I do have one comment: +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + let Uses = [R0] in + def ATOMIC_LOAD_ADD_I32 : Pseudo< The "let Uses = [R0]" is not needed. The pseudo instruction will be expanded like this later: + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + .addReg(ptrA).addReg(ptrB); + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) + .addReg(incr).addReg(dest); + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); The se...

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I...

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const TargetRegisterClass *RC = > is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; > > but I kept...

...patch attached... Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; > > > unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > > > I tried something like that yesterday: > > > > const TargetRegisterClass *RC = > > is64bit ? &PPC::GPRCRegClass : &PP...

...I), MI->getOperand(0).getReg()) + .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) + .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); + } + else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || + MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { + bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; + + unsigned dest = MI->getOperand(0).getReg(); + unsigned ptrA = MI->getOperand(1).getReg(); + unsigned ptrB = MI->getOperand(2).getReg(); + unsigned incr = MI->getOperand(3).getReg(); + + MachineBasicBlock *loopMBB = new...

...I), MI->getOperand(0).getReg()) + .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) + .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); + } + else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || + MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { + bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; + + unsigned dest = MI->getOperand(0).getReg(); + unsigned ptrA = MI->getOperand(1).getReg(); + unsigned ptrB = MI->getOperand(2).getReg(); + unsigned incr = MI->getOperand(3).getReg(); + + MachineBasicBlock *loopMBB = new...

...{ > >> + let Uses = [R0] in > >> + def ATOMIC_LOAD_ADD_I32 : Pseudo< > >> > >> The "let Uses = [R0]" is not needed. The pseudo instruction will be > >> expanded like this later: > >> > >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > >> + .addReg(ptrA).addReg(ptrB); > >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > >> + .addReg(incr).addReg(dest); > >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) &g...

...> Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: >>> Evan Cheng wrote: >>>> How about? >>>> >>>> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >>>> &PPC:G8RCRegClass; >>>> unsigned TmpReg = RegInfo.createVirtualRegister(RC); >>> >>> I tried something like that yesterday: >>> >>> const TargetRegisterClass *RC = >>> is64bit ? &PPC::GPRCR...

...t? Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h (revision 48879) +++ lib/Target/X86/X86Subtarget.h (working copy) @@ -144,9 +144,12 @@ std::string getDataLayout() const { const char *p; - if (is64Bit()) - p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128"; - else { + if (is64Bit()) { + if (isTargetDarwin()) + p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128"; + else + p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:32:32"; + }...

...et.h > =================================================================== > --- lib/Target/X86/X86Subtarget.h (revision 48879) > +++ lib/Target/X86/X86Subtarget.h (working copy) > @@ -144,9 +144,12 @@ > > std::string getDataLayout() const { > const char *p; > - if (is64Bit()) > - p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128"; > - else { > + if (is64Bit()) { > + if (isTargetDarwin()) > + p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128"; > + else > + p = "e-p:64:64-s:64-f64:64:6...