search for: is32bit

...er = 1 in { + let Defs = [WIM] in + def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf), + "#EH_SJLJ_SETJMP32", + [(set i32:$dst, (SPsjlj_setjmp ADDRri:$buf))]>, + Requires<[Is32Bit]>; + def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf), + "#EH_SJLJ_SETJMP32", + [(set i32:$dst, (SPsjlj_setjmp ADDRrr:$buf))]>, + Requires<[Is32Bit]>; + let isTermi...

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

...; > ..... > } > > class MyRegisterClass : RegisterClass<...> { > let RCInfos = [RCInfo32, RCInfo64] > } With the RCInfo data, the new register class definition would be something like class MyRegisterClass : RegisterClass<...> { let RCInfos = HwModeSelect<[Is32Bit, Is64Bit, Is128Bit], [RCInfo32, RCInfo64, RCInfo128]>; } In either case, aggregating the info in a RCInfo class would require additional changes in TableGen so that it picks up the size/alignment/type data from the RCInfos list, instead of from individual memb...

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set