Displaying 6 results from an estimated 6 matches for "irsubreg".
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irsubregs
2012 Mar 28
2
[LLVMdev] Remove subreg copies
Hi,
I'm facing a problem in my BE while trying to remove certain copies.
Here is a code snippet which I would like to optimize
%vreg1<def> = READF32r; vRRegs:%vreg1
%vreg2<def> = COPY %vreg1:rsub_h; iRSubRegs:%vreg2 vRRegs:%vreg1
%vreg3<def> = COPY %vreg1:rsub_l; iRSubRegs:%vreg3 vRRegs:%vreg1
This code produces subreg-to-subreg copies but I would like to have
direct uses of vreg1's subregisters instead.
I tried to add RAhints in order to form identity copies (vreg1 and
vreg2/3 should be a...
2012 Mar 28
0
[LLVMdev] Remove subreg copies
...opard <ivanllopard at gmail.com> wrote:
> Hi,
>
> I'm facing a problem in my BE while trying to remove certain copies.
> Here is a code snippet which I would like to optimize
>
> %vreg1<def> = READF32r; vRRegs:%vreg1
> %vreg2<def> = COPY %vreg1:rsub_h; iRSubRegs:%vreg2 vRRegs:%vreg1
> %vreg3<def> = COPY %vreg1:rsub_l; iRSubRegs:%vreg3 vRRegs:%vreg1
>
> This code produces subreg-to-subreg copies but I would like to have
> direct uses of vreg1's subregisters instead.
> I tried to add RAhints in order to form identity copies (vreg1...
2012 Mar 14
2
[LLVMdev] Data/Address registers
...t = (outs AGRegs:$dst);
dag InOperandList = (ins AGRegs:$a, i16imm:$b);
list<dag> Pattern = [(set AGRegs:$dst, (add AGRegs:$a, imm:$b))];
...
}
def DADDri { // Pattern Pat
dag PatternToMatch = (add LSubRegs:$a, imm:$b);
list<dag> ResultInstrs = [(asrsat (asextr (sextr iRSubRegs:$a),
(XLoadImm imm:$b)), (i16 0))];
}
where asrsat has LSubRegs as its output operand. Both patterns have the
same complexity and they are located at different scopes. For these two
patterns, tblgen is producing the following isel opcodes:
/*3244*/ /*Scope*/ 20, /*->3265*/
/*3245*/...
2012 Mar 14
0
[LLVMdev] Data/Address registers
...dag InOperandList = (ins AGRegs:$a, i16imm:$b);
> list<dag> Pattern = [(set AGRegs:$dst, (add AGRegs:$a, imm:$b))];
> …
> }
>
> def DADDri { // Pattern Pat
> dag PatternToMatch = (add LSubRegs:$a, imm:$b);
> list<dag> ResultInstrs = [(asrsat (asextr (sextr iRSubRegs:$a), (XLoadImm imm:$b)), (i16 0))];
> }
>
> where asrsat has LSubRegs as its output operand. Both patterns have the same complexity and they are located at different scopes. For these two patterns, tblgen is producing the following isel opcodes:
>
> /*3244*/ /*Scope*/ 20, /*-...
2012 Mar 07
0
[LLVMdev] Data/Address registers
On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi Jim,
>
> Thanks for your response.
>
> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>> Hi Ivan,
>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I'm facing a problem in llvm while porting it
2012 Mar 07
2
[LLVMdev] Data/Address registers
Hi Jim,
Thanks for your response.
Le 06/03/2012 22:54, Jim Grosbach a écrit :
> Hi Ivan,
> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi,
>>
>> I'm facing a problem in llvm while porting it to a new target and I'll
>> need some support.
>> We have 2 kind of register, one for general purposes (i.e.