search for: irreversible

Displaying 20 results from an estimated 78 matches for "irreversible".

2006 Apr 06
3
Irreversible Migrations
Hi, To make a migration irreversable, one has to execute "raise IrreversibleMigration". This is how it''s documented everywhere. However, when I do that, I get this: rake aborted! uninitialized constant IrreversibleMigration This is the migration (the file is called 022_ldap_fix.rb): class LdapFix < ActiveRecord::Migration def self.up execute File.o...
2007 Apr 12
7
Looking for a good disk exerciser
I recently added a Seagate 400Gb SATA drive to my system, and it has been behaving strangely since I put it in. for one thing, the BIOS S.M.A.R.T. came up with a warning the last time I booted with it enabled, saying that I should backup my data and replace the disk (!). I still have not made any irreversible data transfers to this drive, and I have some time yet to take it back, but I'd like to know for sure that it needs it, or at least have some reasonable evidence of failure. What is a good program out there that exercises a disk to give some assurance of errors or lack thereof? Thanks. Mark...
2015 Jun 17
8
[Bug 11338] New: Rsync Crash - Segmentation fault
https://bugzilla.samba.org/show_bug.cgi?id=11338 Bug ID: 11338 Summary: Rsync Crash - Segmentation fault Product: rsync Version: 3.1.1 Hardware: x64 OS: Linux Status: NEW Severity: normal Priority: P5 Component: core Assignee: wayned at samba.org Reporter:
2008 Apr 13
4
Replay-gain
Hello everyone, I'm new to this flac thing (started about a week ago) but I have read a lot about flac and replaygain. As far as I understand it, replaygain is lossless in the sense that I can tell my player to ignore the settings or I can even use foobar2000 to remove the tags entirely, hence getting back to the original audio. If that is the case, why is there a warning in the foobar2000
2016 Mar 23
3
Need help with code generation
...n provide a protection for those who wants a 100% crash-free-ness (although I doubt about how effective it is from the user's point of view compared to other components which have crash bugs as discussed in the thread.) People who are in this thread seem to believe that the design choice is not irreversible or will reach to a point where it is irreversible because we will have written too much code with the design, so we won't be able to "fix" any crash "bugs" in future. That is not the case. We can at least provide a new pass anytime to rigorously check any user input. Whether...
2008 Apr 15
0
Replay-gain
...used foobar200, but that message you're seeing implies that if checked, the scaling-factor will be applied to the audio data before it is encoded in the new format (mp3, in your case). Hence the audio will be alterred and due to quantization (ie, rounding errors) it is in the mathematical sense irreversible. > I used EAC and AutoFLAC to rip my CD collection. In the EAC > command line options for flac.exe, I added the --replay-gain parameter > and in the AutoFLAC setup, I enabled the "Add Replaygain" checkbox. > I just downloaded foobar2000 and I can see that the replaygain >...
2016 Mar 23
0
Need help with code generation
...on for those who wants a 100% crash-free-ness (although I > doubt about how effective it is from the user's point of view compared to > other components which have crash bugs as discussed in the thread.) People > who are in this thread seem to believe that the design choice is not > irreversible or will reach to a point where it is irreversible because we > will have written too much code with the design, so we won't be able to > "fix" any crash "bugs" in future. That is not the case. We can at least > provide a new pass anytime to rigorously check any user...
2019 Sep 17
2
[PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > The GPUs found on Tegra SoCs have registers that can be used to read the > WPR configuration. Use these registers instead of reaching into the > memory controller's register space to read the same information. > >
2010 Feb 05
4
Compressing Maildir mails on delivery
Now supported by v2.0. Also as a patch to v1.2: http://dovecot.org/patches/1.2/zlib-compress.diff I'm not really sure if I should commit it to v1.2 code tree. The code contains ugly copy&pasted io_stream_copy() and v1.2 is supposed to be feature complete.. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature
2007 Feb 20
4
Best way to implement syntax sugar?
Hi! I''m *very* new to rails, I just dove in about a month ago and I''m loving it. One thing I decided I immediately wanted to do, was shorten the number of keystrokes neccessary to URI, HTML, or Jscript encode something. The project I''ve come into already has helpers defined for this. Right now, what I''ve done is: alias h! string_esacpe_html alias u!
2013 Apr 16
7
[Bug 9798] New: rsync crash with SIGSEGV when read time out happens
.../bugzilla.samba.org/attachment.cgi?id=8774 core file rsync crashed with the following backtrace when read timeout happened. (gdb) bt #0 ascii_internal_loop (step=0x80a2ee8, step_data=0x80a3d24, inptrp=0xbfffb05c, inend=0xbfffbd48 "\n", outptrp=0xbfffaf84, outend=0x80a5018 "", irreversible=0xbfffaf88) at loop.c:282 #1 0xb7f9cbb2 in __gconv_transform_ascii_internal (step=0x80a2ee8, data=0x80a2fe8, inptrp=0xbfffb05c, inend=0xbfffbd48 "\n", outbufstart=0x0, irreversible=0xbfffb018, do_flush=0, consume_incomplete=0) at skeleton.c:483 #2 0xb7f99ec7 in __gconv (cd=0x80a2fe...
2016 Oct 28
0
Understanding and Cleaning Up Machine Instruction Bundles
...could not find any mails > documenting this, so it would be nice if some people could chime in here if > that was indeed the plan. That sounds wrong. To reiterate, a Hexagon's packet is not equivalent to a sequence of individual instructions. Packetization on Hexagon can be considered irreversible. This may not be the case on other architectures. Iterating over operands within a bundle without additional information seems random at best. -Krzysztof
2004 Nov 17
1
Re: variations on the theme of survSplit
...n[s] for this > survival-splitting business, as I do, this 'survcut' function below > might be helpful. > It is not an elegant nor efficient function but it works, at least for > some examples below. > Ditto the following, for the case where there are multiple time-varying (irreversible) binary covariates, here slicing as coarsely as possible. # # Create dataset for survival analysis with time-dependent covariate # Gill-Anderson model # x <- data.frame(onset=c(46, 32, 53, 76, 64, 43), case=c(1,1,1,0,0,0), ooph=c(NA, 30, 38, 50, NA, NA),...
2018 Dec 04
2
MatchLoadCombine(): handling for vectorized loop.
...done so late but found in the commit message (b52af07 / r293036) that there had been a discussion where this had intentionally been addressed late: "...We came to the conclusion that we want to do this transformation late in the pipeline because in presence of atomic loads load widening is irreversible transformation and it might hinder other optimizations..." The loop vectorizer looks at such a loop and thinks the scalar loop costs 13 and VF=4 costs 5. The cost for the vectorized loop is about right, but the scalar loop becomes much better with the help of MatchLoadCombine(): just 2 in...
2019 Sep 16
0
[PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
From: Thierry Reding <treding at nvidia.com> The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding <treding at nvidia.com> --- .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +-
2013 Dec 06
1
[LLVMdev] [RFC] CGContext skeleton implementation
On Thu, Dec 5, 2013 at 7:36 PM, Andrew Trick <atrick at apple.com> wrote: > It might nice if scalaropts did not need to link against libTarget—we > could easily avoid introducing more dependence on libTarget if that’s a > goal. > We already have that state today in the overwhelming majority of the cases. The pass manager built by the PassManagerBuilder doesn't need a target
2020 Apr 08
2
Questions about vscale
...e, does it contrary to the philosophy of LLVM IR as reasonably target-independent IR? I do not get the point of your argument. Hi Kai, Don't worry about target-independent IR in your design of intermediate passes or lowering. By the time the front-end lowers to LLVM IR, it already has, often irreversible, target-specific knowledge in it. If by some stroke of luck that doesn't happen, then using "<vscale x anything>" is enough indication that you should not try to lower that onto a target that it wasn't specifically aimed at. No one expects the middle-end to be target-neutr...
2020 Jan 15
2
[PITCH] Improvements to LLVM Decision Making
On 01/15, James Henderson via llvm-dev wrote: > One other thought: any formal review period needs to be long enough for > people to contribute to if they have any annual leave from work or > whatever. For example, if the review period were to be set to two weeks, > I'd have missed proposals made at the start of roughly 2-3 different 2 week > periods last year. It would have been
2019 Sep 17
0
[PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
On Tue, Sep 17, 2019 at 01:49:57PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > > > From: Thierry Reding <treding at nvidia.com> > > > > The GPUs found on Tegra SoCs have registers that can be used to read the > > WPR configuration. Use these registers instead of reaching into the >
2019 Sep 11
2
Load combine pass
...tatus of load widening. It seems there is no load widening on IR at all. // Paweł On Wed, Oct 5, 2016 at 1:49 PM Artur Pilipenko via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Philip and I talked about this is person. Given the fact that load > widening in presence of atomics is irreversible transformation we agreed > that we don't want to do this early. For now it can be implemented as a > peephole optimization over machine IR. MIR is preferred here because X86 > backend does GEP reassociation at MIR level and it can make information > about addresses being adjacent av...