search for: irreversable

Hi, To make a migration irreversable, one has to execute "raise IrreversibleMigration". This is how it''s documented everywhere. However, when I do that, I get this: rake aborted! uninitialized constant IrreversibleMigration This is the migration (the file is called 022_ldap_fix.rb): class LdapFix < ActiveRecor...

I recently added a Seagate 400Gb SATA drive to my system, and it has been behaving strangely since I put it in. for one thing, the BIOS S.M.A.R.T. came up with a warning the last time I booted with it enabled, saying that I should backup my data and replace the disk (!). I still have not made any irreversible data transfers to this drive, and I have some time yet to take it back, but I'd

https://bugzilla.samba.org/show_bug.cgi?id=11338 Bug ID: 11338 Summary: Rsync Crash - Segmentation fault Product: rsync Version: 3.1.1 Hardware: x64 OS: Linux Status: NEW Severity: normal Priority: P5 Component: core Assignee: wayned at samba.org Reporter:

Hello everyone, I'm new to this flac thing (started about a week ago) but I have read a lot about flac and replaygain. As far as I understand it, replaygain is lossless in the sense that I can tell my player to ignore the settings or I can even use foobar2000 to remove the tags entirely, hence getting back to the original audio. If that is the case, why is there a warning in the foobar2000

On Tue, Mar 22, 2016 at 10:33 PM, David Blaikie <dblaikie at gmail.com> wrote: > > > On Tue, Mar 22, 2016 at 1:29 PM, Rui Ueyama <ruiu at google.com> wrote: > >> On Tue, Mar 22, 2016 at 9:19 PM, David Blaikie <dblaikie at gmail.com> >> wrote: >> >>> >>> >>> On Tue, Mar 22, 2016 at 1:15 PM, Rui Ueyama <ruiu at

On Sun, Apr 13, 2008 at 02:10:51AM -0500, Charles Velasquez wrote: > If that is the case, why is there a warning in the foobar2000 > converter dialogue box stating that "applying ReplayGain adjustment > during conversion will irreversibly alter data in encoded file, > unlike ReplayGain scan after encode"? ReplayGain, as the name implies, works by calculating a scaling-factor

On Wed, Mar 23, 2016 at 3:52 AM, Rui Ueyama <ruiu at google.com> wrote: > On Tue, Mar 22, 2016 at 10:33 PM, David Blaikie <dblaikie at gmail.com> > wrote: > >> >> >> On Tue, Mar 22, 2016 at 1:29 PM, Rui Ueyama <ruiu at google.com> wrote: >> >>> On Tue, Mar 22, 2016 at 9:19 PM, David Blaikie <dblaikie at gmail.com> >>>

On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > The GPUs found on Tegra SoCs have registers that can be used to read the > WPR configuration. Use these registers instead of reaching into the > memory controller's register space to read the same information. > >

Now supported by v2.0. Also as a patch to v1.2: http://dovecot.org/patches/1.2/zlib-compress.diff I'm not really sure if I should commit it to v1.2 code tree. The code contains ugly copy&pasted io_stream_copy() and v1.2 is supposed to be feature complete.. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature

Hi! I''m *very* new to rails, I just dove in about a month ago and I''m loving it. One thing I decided I immediately wanted to do, was shorten the number of keystrokes neccessary to URI, HTML, or Jscript encode something. The project I''ve come into already has helpers defined for this. Right now, what I''ve done is: alias h! string_esacpe_html alias u!

https://bugzilla.samba.org/show_bug.cgi?id=9798 Summary: rsync crash with SIGSEGV when read time out happens Product: rsync Version: 3.0.2 Platform: All OS/Version: All Status: NEW Severity: critical Priority: P5 Component: core AssignedTo: wayned at samba.org ReportedBy: vijunag at

On 10/27/2016 4:33 PM, Matthias Braun via llvm-dev wrote: > > In fact I am not sure why you would even wait with the finalization and do it > in a separate pass rather than doing it immediately after forming the bundle. > Using the pass today does not even work as the MachineVerifier will reject the > intermediate unfinalized state (missing internal read markers). I'd suggest to

Danardono <daodao99 at student.umu.se> wrote: > > While waiting for 2.1, for those who need function[s] for this > survival-splitting business, as I do, this 'survcut' function below > might be helpful. > It is not an elegant nor efficient function but it works, at least for > some examples below. > Ditto the following, for the case where there are multiple

Hi Eli, On 2018-12-04 00:37, Friedman, Eli wrote: > On 12/3/2018 8:20 AM, Jonas Paulsson wrote: >> Hi, >> >> I have noticed some loops that build a wider element by loading small >> elements, zero-extending them, shifting them (with different amounts) >> to then 'or' them all together. They are either equivalent of a wider >> load, or to that of a

From: Thierry Reding <treding at nvidia.com> The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding <treding at nvidia.com> --- .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +-

On Thu, Dec 5, 2013 at 7:36 PM, Andrew Trick <atrick at apple.com> wrote: > It might nice if scalaropts did not need to link against libTarget—we > could easily avoid introducing more dependence on libTarget if that’s a > goal. > We already have that state today in the overwhelming majority of the cases. The pass manager built by the PassManagerBuilder doesn't need a target

On Wed, 8 Apr 2020 at 04:23, Kai Wang <kai.wang at sifive.com> wrote: > If we apply the type system pointed out by Renato, is the vector type <vscale x 1 x i16> legal? If we decide that <vscale x 1 x i16> is a fundamentally impossible type, does it contrary to the philosophy of LLVM IR as reasonably target-independent IR? I do not get the point of your argument. Hi Kai,

On 01/15, James Henderson via llvm-dev wrote: > One other thought: any formal review period needs to be long enough for > people to contribute to if they have any annual leave from work or > whatever. For example, if the review period were to be set to two weeks, > I'd have missed proposals made at the start of roughly 2-3 different 2 week > periods last year. It would have been

On Tue, Sep 17, 2019 at 01:49:57PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > > > From: Thierry Reding <treding at nvidia.com> > > > > The GPUs found on Tegra SoCs have registers that can be used to read the > > WPR configuration. Use these registers instead of reaching into the >

Hi, Can I ask what is the status of load widening. It seems there is no load widening on IR at all. // Paweł On Wed, Oct 5, 2016 at 1:49 PM Artur Pilipenko via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Philip and I talked about this is person. Given the fact that load > widening in presence of atomics is irreversible transformation we agreed > that we don't want to do