search for: irq_to_desc

Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -296,7 +296,7 @@ static void hpet_msi_ack(unsigned int ir { struct irq_desc *desc = irq_to_desc(irq); - irq_complete_move(&desc); + irq_complete_move(desc); move_native_irq(irq); ack_APIC_irq(); } --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -513,9 +513,8 @@ static void send_cleanup_vector(struct i cfg->move_in_progress = 0; } -void irq_comple...

...| irq_enter() { 1) | rcu_irq_enter() { 1) 0.102 us | rcu_exit_nohz(); 1) 0.431 us | } 1) 0.064 us | idle_cpu(); 1) 1.152 us | } 1) | __xen_evtchn_do_upcall() { 1) 0.119 us | irq_to_desc(); 1) | handle_edge_irq() { 1) 0.107 us | _raw_spin_lock(); 1) | ack_dynirq() { 1) | evtchn_from_irq() { 1) | info_for_irq() { 1) | irq_get_irq_data() {...

...b/xen/arch/arm/vgic.c index f9c1a6b..c5370d5 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -676,9 +676,14 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq, int virtual) n->irq = irq; n->priority = priority; if (!virtual) + { n->desc = irq_to_desc(irq); - else + cpumask_clear(&n->eoimask); + /* Assume we received the IRQ on the current pcpu */ + cpumask_set_cpu(smp_processor_id(), &n->eoimask); + } else { n->desc = NULL; + } /* the irq is enabled */ if ( rank->ienable &am...

...anyway, doing - * this is pointless. So for now just discard the write (also - * saving us from having to determine the matching irq_desc). - */ + m_desc = virt_to_msi_desc(entry->pdev, virt); + if ( !m_desc || m_desc->irq < 0 ) + goto out; + + desc = irq_to_desc(m_desc->irq); + if ( !desc ) + goto out; + spin_lock_irqsave(&desc->lock, flags); + + if ( !desc->msi_desc ) + goto unlock; + orig = readl(virt); - val &= ~PCI_MSIX_VECTOR_BITMASK; - val |= orig & PCI_MSIX_VECTOR_BITMASK; + + /* + * Do...

...eg[irq] = priority; + +} + /* Program the GIC to route an interrupt */ static int gic_route_irq(unsigned int irq, bool_t level, unsigned int cpu_mask, unsigned int priority) { - volatile unsigned char *bytereg; - uint32_t cfg, edgebit; struct irq_desc *desc = irq_to_desc(irq); unsigned long flags; @@ -202,22 +226,7 @@ static int gic_route_irq(unsigned int irq, bool_t level, /* Disable interrupt */ desc->handler->shutdown(desc); - /* Set edge / level */ - cfg = GICD[GICD_ICFGR + irq / 16]; - edgebit = 2u << (2 * (irq % 16)); -...

...igned char key) +{ + int irq; + printk("''%c'' pressed -> dumping GIC state\n", key); + + for ( irq = 0; irq < gic.lines; irq++ ) + { + const char *type; + int type_nr, enable, pend, active, priority, target; + struct irq_desc *desc = irq_to_desc(irq); + uint8_t *bytereg; + uint32_t wordreg; + + bytereg = (uint8_t *) (GICD + GICD_ITARGETSR); + target = bytereg[irq]; + + bytereg = (uint8_t *) (GICD + GICD_IPRIORITYR); + priority = bytereg[irq]; + + switch ( irq ) + { + case 0 ......

...irq_desc *desc) +{ + struct msi_msg msg; - return 0; + msi_compose_msg(desc, &msg); + write_msi_msg(desc->msi_desc, &msg); } int msi_free_irq(struct msi_desc *entry) @@ -1018,19 +1058,20 @@ static void dump_msi(unsigned char key) { struct irq_desc *desc = irq_to_desc(irq); const struct msi_desc *entry; - u32 addr, data; + u32 addr, data, dest32; + int mask; + struct msi_attrib attr; unsigned long flags; char type; spin_lock_irqsave(&desc->lock, flags); entry = desc->msi_desc;...

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine

...static vmask_t *irq_get_used_vector_mask { vmask_t *ret = NULL; - if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_GLOBAL ) + if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_GLOBAL || + opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_PERDEV_GLOBAL ) { struct irq_desc *desc = irq_to_desc(irq); diff -r 84e4d183fa8b -r 6671fc79717a xen/drivers/passthrough/amd/pci_amd_iommu.c --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -238,6 +238,21 @@ int __init amd_iov_detect(void) } if ( !amd_iommu_perdev_intremap ) pr...

I''m afraid this series is rather a grab bag and it is distressingly large at this stage. With this series I can boot an Xgene board until it fails to find its SATA controller. This is a dom0 issue for which patches are pending from APM (/me nudges Anup). As well as the APM specific platform stuff there are also some generic improvements which were either necessary or useful during this

Hi, This is the fifth version of this patch series. With the Versatile Express TC2, it''s possible to boot only with A7 or A15. If the user choose to boot with only A7, the CPU ID will start at 0x100. As Xen relies on it to set the logical ID and the GIC, it won''t be possible to use Xen with this use case. This patch series is divided in 3 parts: - Patch 1: prepare Xen

I''ve been trying for several days to get a xen dom0 booting as described on Boris Derzhavets blog. I have been able to boot Jeremy Fitzhardinge''s pv_ops kernel under xen, but my X server wouldn''t start so I''ve been trying to get Andrew Lyon''s rebased opensuse patches to work. I have asked for help in the freenode ##xen channel but they

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> Hi all, This series does two major things: 1. It converts the bulk of the implementation to C, and makes the "small ticket" and "large ticket" code common. Only the actual size-dependent asm instructions are specific to the ticket size. The resulting generated asm is very similar to the current

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> Hi all, This series does two major things: 1. It converts the bulk of the implementation to C, and makes the "small ticket" and "large ticket" code common. Only the actual size-dependent asm instructions are specific to the ticket size. The resulting generated asm is very similar to the current

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> Hi all, This series does two major things: 1. It converts the bulk of the implementation to C, and makes the "small ticket" and "large ticket" code common. Only the actual size-dependent asm instructions are specific to the ticket size. The resulting generated asm is very similar to the current

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> Changes since last posting: (Raghavendra K T) [ - Rebased to linux-3.3-rc6. - used function+enum in place of macro (better type checking) - use cmpxchg while resetting zero status for possible race [suggested by Dave Hansen for KVM patches ] ] This series replaces the existing paravirtualized spinlock mechanism with a

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> Changes since last posting: (Raghavendra K T) [ - Rebased to linux-3.3-rc6. - used function+enum in place of macro (better type checking) - use cmpxchg while resetting zero status for possible race [suggested by Dave Hansen for KVM patches ] ] This series replaces the existing paravirtualized spinlock mechanism with a

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> This series replaces the existing paravirtualized spinlock mechanism with a paravirtualized ticketlock mechanism. (targeted for 3.5 window) Changes in V7: - Reabsed patches to 3.4-rc3 - Added jumplabel split patch (originally from Andrew Jones rebased to 3.4-rc3 - jumplabel changes from Ingo and Jason taken and now using

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> This series replaces the existing paravirtualized spinlock mechanism with a paravirtualized ticketlock mechanism. (targeted for 3.5 window) Changes in V7: - Reabsed patches to 3.4-rc3 - Added jumplabel split patch (originally from Andrew Jones rebased to 3.4-rc3 - jumplabel changes from Ingo and Jason taken and now using

This series replaces the existing paravirtualized spinlock mechanism with a paravirtualized ticketlock mechanism. The series provides implementation for both Xen and KVM. The current set of patches are for Xen/x86 spinlock/KVM guest side, to be included against -tip. I 'll be sending a separate patchset for KVM host based on kvm tree. Please note I have added the below performance result