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The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/base.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/secboot/base.c b/drm/nouveau/nvkm/subdev/secboot/base.c index b718ba79177c..05c62549...

...OOT_FALCON_RESERVED = 1, + NVKM_SECBOOT_FALCON_FECS = 2, + NVKM_SECBOOT_FALCON_GPCCS = 3, + NVKM_SECBOOT_FALCON_END = 4, + NVKM_SECBOOT_FALCON_INVALID = 0xffffffff, +}; + +/** + * @falcon_id: falcon that will perform secure boot + * @base: base IO address of the falcon performing secure boot + * @irq_mask: IRQ mask of the falcon performing secure boot + * @enable_mask: enable mask of the falcon performing secure boot +*/ +struct nvkm_secboot { + const struct nvkm_secboot_func *func; + struct nvkm_subdev subdev; + + u32 base; + u32 irq_mask; + u32 enable_mask; +}; +#define nvkm_secboot(p) container...

...nc = func; > + Move these two after the switch statement ? > + /* setup the performing falcon's base address and masks */ > + switch (func->boot_falcon) { > + case NVKM_SECBOOT_FALCON_PMU: > + sb->base = 0x10a000; > + sb->irq_mask = 0x1000000; > + sb->enable_mask = 0x2000; > + break; > + default: > + nvdev_error(device, "invalid secure boot falcon\n"); > + return -EINVAL; > + }; > + > + nvkm_info(&sb->subdev,...

Hi Konrad / Yu Ke, I have tried konrad''s master tree: commit 329408d788f62629131ea28c112e973878d52c9e Merge: e370fe2 773f8cf Author: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Date: Thu May 19 14:37:32 2011 -0400 Merge branch ''linux-next'' With a xen-4.1.0 hypervisor, on my AMD x6 phenom. Curious if Xen Power Management would work... Output of all xenpm

...rrectly, so it's correct as-is. > >> + /* setup the performing falcon's base address and masks */ >> + switch (func->boot_falcon) { >> + case NVKM_SECBOOT_FALCON_PMU: >> + sb->base = 0x10a000; >> + sb->irq_mask = 0x1000000; >> + sb->enable_mask = 0x2000; >> + break; >> + default: >> + nvdev_error(device, "invalid secure boot falcon\n"); >> + return -EINVAL; >> + }; >> + >> +...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

Hi, Keir, These patches are rebased version of Yunhong''s original patches, which were sent out before XEN 3.2 was released. These patches enable MSI support and limited MSI-X support in XEN. Here is the original description of the patches from Yunhong''s mail. The basic idea including: 1) Keep vector global resource owned by xen, while split pirq into per-domain

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

This is the initial proposal for a paravirtualized IOMMU device using virtio transport. It contains a description of the device, a Linux driver, and a toy implementation in kvmtool. With this prototype, you can translate DMA to guest memory from emulated (virtio), or passed-through (VFIO) devices. In its simplest form, implemented here, the device handles map/unmap requests from the guest. Future

This is the initial proposal for a paravirtualized IOMMU device using virtio transport. It contains a description of the device, a Linux driver, and a toy implementation in kvmtool. With this prototype, you can translate DMA to guest memory from emulated (virtio), or passed-through (VFIO) devices. In its simplest form, implemented here, the device handles map/unmap requests from the guest. Future