search for: iowrite32_n

...; - return ((volatile u32 *)chan->user)[addr / 4]; + return ioread32_native(chan->user + addr); } void _nouveau_fifo_channel_wr32(struct nouveau_object *object, u32 addr, u32 data) { struct nouveau_fifo_chan *chan = (void *)object; - ((volatile u32 *)chan->user)[addr / 4] = data; + iowrite32_native(data, chan->user + addr); } static int -- 1.7.8.6

...ing the fifo */ - struct drm_local_map *user; + void __iomem *user; uint32_t user_get; uint32_t user_put; @@ -1047,11 +1047,8 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *, #endif /* !ioread32_native */ /* channel control reg access */ -#define nvchan_wr32(reg, val) \ - iowrite32_native((val), \ - (void __force __iomem *)chan->user->handle + (reg)) -#define nvchan_rd32(reg) \ - ioread32_native((void __force __iomem *)chan->user->handle + (reg)) +#define nvchan_wr32(reg, val) iowrite32_native((val), chan->user + (reg)) +#define nvchan_rd32(reg) ioread32_native...

...oid __force __iomem *)mem); > - else > + else { > *mem = val; > + nv_cpu_cache_flush_area(mem, 2); > + } > } > > u32 > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) > mem = &mem[index]; > if (is_iomem) > iowrite32_native(val, (void __force __iomem *)mem); > - else > + else { > *mem = val; > + nv_cpu_cache_flush_area(mem, 4); > + } This looks rather like a sledgehammer to me. Effectively this turns nvbo into an uncached buffer. With additional overhead of constantly flushing caches. Wouldn...

...= ((struct evo_object *)object)->iomem; return ioread32_native(iomem + addr); } static void nv50_evo_wr32(struct nouveau_object *object, u32 addr, u32 data) { - void __iomem *iomem = object->oclass->ofuncs->rd08; + void __iomem *iomem = ((struct evo_object *)object)->iomem; iowrite32_native(data, iomem + addr); } @@ -60,7 +65,7 @@ nv50_evo_channel_del(struct nouveau_channel **pevo) nouveau_bo_ref(NULL, &evo->push.buffer); if (evo->object) - iounmap(evo->object->oclass->ofuncs); + iounmap(((struct evo_object *)evo->object)->iomem); kfree(evo...

...nv_cpu_cache_flush_area(mem, 2); > > > + } > > > } > > > > > > u32 > > > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) > > > mem = &mem[index]; > > > if (is_iomem) > > > iowrite32_native(val, (void __force __iomem *)mem); > > > - else > > > + else { > > > *mem = val; > > > + nv_cpu_cache_flush_area(mem, 4); > > > + } > > > > This looks rather like a sledgehammer to me. Effectively this turns nvbo > > into an u...

...cpu_cache_flush_area(mem, 2); >> > + } >> > } >> > >> > u32 >> > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) >> > mem = &mem[index]; >> > if (is_iomem) >> > iowrite32_native(val, (void __force __iomem *)mem); >> > - else >> > + else { >> > *mem = val; >> > + nv_cpu_cache_flush_area(mem, 4); >> > + } >> >> This looks rather like a sledgehammer to me. Effectively this turns nvbo &gt...

...determine classes of subdev/engines */ if (detect) { /* switch mmio to cpu's native endianness */ -#ifndef __BIG_ENDIAN - if (ioread32_native(map + 0x000004) != 0x00000000) { -#else - if (ioread32_native(map + 0x000004) == 0x00000000) { -#endif + if (!nvkm_device_endianness(map)) { iowrite32_native(0x01000001, map + 0x000004); ioread32_native(map); + if (!nvkm_device_endianness(map)) { + nvdev_error(device, + "GPU not supported on big-endian\n"); + ret = -ENOSYS; + goto done; + } } /* read boot0 and strapping information */ -- 2.25.3

...&mem[index]; if (is_iomem) iowrite16_native(val, (void __force __iomem *)mem); - else + else { *mem = val; + nv_cpu_cache_flush_area(mem, 2); + } } u32 @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) mem = &mem[index]; if (is_iomem) iowrite32_native(val, (void __force __iomem *)mem); - else + else { *mem = val; + nv_cpu_cache_flush_area(mem, 4); + } } static struct ttm_tt * -- 1.9.2

...rm_device *dev, unsigned offset) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - return ioread32_native(dev_priv->fb + offset); -} - -static inline void nv_wf32(struct drm_device *dev, unsigned offset, u32 val) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - iowrite32_native(val, dev_priv->fb + offset); -} - /* PRAMIN access */ static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) { diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c index 295b876..6f55f55 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hw.c +++...

Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_gem.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 64e59fb..75cae79 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -595,7 +595,7 @@

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 8ebbe1656..17676c75a 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 8ebbe1656..17676c75a 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++

...e { > > *mem = val; > > + nv_cpu_cache_flush_area(mem, 2); > > + } > > } > > > > u32 > > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) > > mem = &mem[index]; > > if (is_iomem) > > iowrite32_native(val, (void __force __iomem *)mem); > > - else > > + else { > > *mem = val; > > + nv_cpu_cache_flush_area(mem, 4); > > + } > > This looks rather like a sledgehammer to me. Effectively this turns nvbo > into an uncached buffer. With additional overhead...

...t;>> > + } >>> > } >>> > >>> > u32 >>> > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) >>> > mem = &mem[index]; >>> > if (is_iomem) >>> > iowrite32_native(val, (void __force __iomem *)mem); >>> > - else >>> > + else { >>> > *mem = val; >>> > + nv_cpu_cache_flush_area(mem, 4); >>> > + } >>> >>> This looks rather like a sledgehammer to me. Eff...

...og there are several repeating errors. log_unaligned: 598 callbacks suppressed Kernel unaligned access at TPC[105d9fb4] nvkm_instobj_wr32+0x14/0x20 [nouveau] Eventually the Xorg session gives up and times out. I'll try and attach some more logs but it appears to have something to do with the iowrite32_native macro on SPARC V9 systems. -- You are receiving this mail because: You are the assignee for the bug. -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/nouveau/attachments/20160707/c6c9e745/attachment.html>

This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when

...32_native((void __force __iomem *)mem); @@ -562,7 +529,7 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) bool is_iomem; u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); - mem = nouveau_bo_mem_index(nvbo, index, mem); + mem += index; if (is_iomem) iowrite32_native(val, (void __force __iomem *)mem); @@ -1492,14 +1459,6 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) dev = drm->dev; pdev = device->dev; - /* - * Objects matching this condition have been marked as force_coherent, - * so use the DMA API for them. - */ - if (!nvxx_device(&dr...

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/engine/device/base.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 8ebbe1656..37589f365 100644 ---

https://bugs.freedesktop.org/show_bug.cgi?id=87554 Bug ID: 87554 Summary: [NV1A] 3.19-rc1 NULL dereference on modprobe in pramin_fini Product: xorg Version: unspecified Hardware: x86 (IA32) OS: Linux (All) Status: NEW Severity: major Priority: medium Component:

...s_iomem) + return ioread32_native((void __force __iomem *)mem); + else + return *mem; +} + +void +nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) +{ + bool is_iomem; + u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); + mem = &mem[index]; + if (is_iomem) + iowrite32_native(val, (void __force __iomem *)mem); + else + *mem = val; +} static struct ttm_backend * nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) { diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index c6143b8..44a7ab5 100644 --- a/drivers/gp...