Displaying 10 results from an estimated 10 matches for "iowrite16_native".
2014 May 19
3
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...c
[...]
> index 0886f47e5244..b9c9729c5733 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
> mem = &mem[index];
> if (is_iomem)
> iowrite16_native(val, (void __force __iomem *)mem);
> - else
> + else {
> *mem = val;
> + nv_cpu_cache_flush_area(mem, 2);
> + }
> }
>
> u32
> @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
> mem = &mem[index];
> if (is_iomem)...
2014 May 19
2
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...t; > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> > > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
> > > mem = &mem[index];
> > > if (is_iomem)
> > > iowrite16_native(val, (void __force __iomem *)mem);
> > > - else
> > > + else {
> > > *mem = val;
> > > + nv_cpu_cache_flush_area(mem, 2);
> > > + }
> > > }
> > >
> > > u32
> > > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouv...
2014 Jun 09
2
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
>> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>> > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
>> > mem = &mem[index];
>> > if (is_iomem)
>> > iowrite16_native(val, (void __force __iomem *)mem);
>> > - else
>> > + else {
>> > *mem = val;
>> > + nv_cpu_cache_flush_area(mem, 2);
>> > + }
>> > }
>> >
>> > u32
>> > @@ -461,8 +463,10 @@ nouveau_bo_wr3...
2014 May 19
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...o.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 0886f47e5244..b9c9729c5733 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
mem = &mem[index];
if (is_iomem)
iowrite16_native(val, (void __force __iomem *)mem);
- else
+ else {
*mem = val;
+ nv_cpu_cache_flush_area(mem, 2);
+ }
}
u32
@@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
mem = &mem[index];
if (is_iomem)
iowrite32_native(val, (void __force __iomem *)mem);...
2014 May 19
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...4..b9c9729c5733 100644
> > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
> > mem = &mem[index];
> > if (is_iomem)
> > iowrite16_native(val, (void __force __iomem *)mem);
> > - else
> > + else {
> > *mem = val;
> > + nv_cpu_cache_flush_area(mem, 2);
> > + }
> > }
> >
> > u32
> > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
> &...
2014 Jun 12
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...m/nouveau/nouveau_bo.c
>>> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>>> > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
>>> > mem = &mem[index];
>>> > if (is_iomem)
>>> > iowrite16_native(val, (void __force __iomem *)mem);
>>> > - else
>>> > + else {
>>> > *mem = val;
>>> > + nv_cpu_cache_flush_area(mem, 2);
>>> > + }
>>> > }
>>> >
>>> > u32
>>> >...
2014 May 19
8
[PATCH 0/4] drm/ttm: nouveau: memory coherency fixes for ARM
This small series introduces TTM helper functions as well as Nouveau hooks that
are needed to ensure buffer coherency on ARM. Most of this series is a
forward-port of some patches Lucas Stach sent last year and that are also
needed for Nouveau GK20A support:
http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html
Another patch takes care of flushing the CPU write-buffer when
2016 Jul 13
1
[PATCH 1/2] ttm: remove special handling of coherent objects
..., m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
-
void
nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
{
bool is_iomem;
u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
- mem = nouveau_bo_mem_index(nvbo, index, mem);
+ mem += index;
if (is_iomem)
iowrite16_native(val, (void __force __iomem *)mem);
@@ -548,7 +515,7 @@ nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
bool is_iomem;
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
- mem = nouveau_bo_mem_index(nvbo, index, mem);
+ mem += index;
if (is_iomem)
return ioread...
2014 Oct 27
4
[PATCH v5 0/4] drm: nouveau: memory coherency on ARM
It has been a couple of months since v4 - apologies for this. v4 has not
received many comments, but this version addresses them and makes a new
attempt at pushing the critical bit for GK20A and Nouveau on ARM in
general.
As a reminder, this series addresses the memory coherency issue that we
are seeing on ARM platforms. Contrary to x86 which invalidates the PCI
caches whenever a write is made by
2014 Jul 08
8
[PATCH v4 0/6] drm: nouveau: memory coherency on ARM
Another revision of this patchset critical for GK20A to operate.
Previous attempts were exclusively using either TTM's regular page allocator or
the DMA API one. Both have their advantages and drawbacks: the page allocator is
fast but requires explicit synchronization on non-coherent architectures,
whereas the DMA allocator always returns coherent memory, but is also slower,
creates a