Displaying 20 results from an estimated 20 matches for "ioresource_prefetch".
2008 Oct 08
8
[PATCH] dom0 linux: Reassign memory resources to device for pci passthrough.
...||
+ (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) {
+ return;
+ }
+
+ if (!res->flags)
+ return;
+
+ switch (resno) {
+ case 8 : /* MMIO Base/Limit */
+ pcibios_resource_to_bus(dev, ®ion, res);
+ if (res->flags & IORESOURCE_MEM &&
+ !(res->flags & IORESOURCE_PREFETCH)) {
+ l = (region.start >> 16) & 0xfff0;
+ l |= region.end & 0xfff00000;
+ } else {
+ l = 0x0000fff0;
+ }
+ pci_write_config_dword(dev, PCI_MEMORY_BASE, l);
+
+ break;
+
+ case 9 : /* Prefetchable MMIO Base/Limit */
+ /* Clear out the upper 32 bits of PREF limit.
+ * If P...
2014 Dec 11
1
[PATCH RFC 3/5] pci: add pci_iomap_range
On Thursday 11 December 2014 21:37:34 Michael S. Tsirkin wrote:
> if (flags & IORESOURCE_MEM) {
> - if (flags & IORESOURCE_CACHEABLE)
> + if (!force_nocache && (flags & IORESOURCE_CACHEABLE))
> return ioremap(start, len);
> return ioremap_nocache(start, len);
> }
>
ioremap
2014 Dec 11
1
[PATCH RFC 3/5] pci: add pci_iomap_range
On Thursday 11 December 2014 21:37:34 Michael S. Tsirkin wrote:
> if (flags & IORESOURCE_MEM) {
> - if (flags & IORESOURCE_CACHEABLE)
> + if (!force_nocache && (flags & IORESOURCE_CACHEABLE))
> return ioremap(start, len);
> return ioremap_nocache(start, len);
> }
>
ioremap
2008 Jun 27
2
PCI device assignment to guests (userspace)
Userspace patches for the pci-passthrough functionality.
The major updates since the last post are:
- Loop to add passthrough devices in pc_init1
- Handle errors in read/write calls
- Allow invocation without irq number for in-kernel irqchip
Other than this, several small things were fixed according to review comments received last time.
2008 Jun 27
2
PCI device assignment to guests (userspace)
Userspace patches for the pci-passthrough functionality.
The major updates since the last post are:
- Loop to add passthrough devices in pc_init1
- Handle errors in read/write calls
- Allow invocation without irq number for in-kernel irqchip
Other than this, several small things were fixed according to review comments received last time.
2008 Sep 27
3
[PATCH 1/6 v3] PCI: export some functions and macros
...+= __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -344,7 +340,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_mem32, res, rom);
}
}
@@ -366,9 +362,6 @@ void __d...
2008 Sep 27
3
[PATCH 1/6 v3] PCI: export some functions and macros
...+= __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -344,7 +340,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_mem32, res, rom);
}
}
@@ -366,9 +362,6 @@ void __d...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [3/4]
...ci_read_base(pf, pci_bar_unknown, res, reg);
+ if (!res->flags)
+ continue;
+
+ size = resource_size(res) * pf->iov->nr_virtfn;
+ res->end = res->start + size - 1;
+ err = pci_bus_alloc_resource(pf->bus, res, size, pf->iov->align,
+ PCIBIOS_MIN_MEM,
+ IORESOURCE_PREFETCH, NULL, NULL);
+ if (err < 0 && (res->flags & IORESOURCE_PREFETCH))
+ err = pci_bus_alloc_resource(pf->bus, res, size,
+ pf->iov->align,
+ PCIBIOS_MIN_MEM,
+ 0, NULL, NULL);
+ if (err) {
+ dev_err(&pf->dev, "can't allocat...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [3/4]
...ci_read_base(pf, pci_bar_unknown, res, reg);
+ if (!res->flags)
+ continue;
+
+ size = resource_size(res) * pf->iov->nr_virtfn;
+ res->end = res->start + size - 1;
+ err = pci_bus_alloc_resource(pf->bus, res, size, pf->iov->align,
+ PCIBIOS_MIN_MEM,
+ IORESOURCE_PREFETCH, NULL, NULL);
+ if (err < 0 && (res->flags & IORESOURCE_PREFETCH))
+ err = pci_bus_alloc_resource(pf->bus, res, size,
+ pf->iov->align,
+ PCIBIOS_MIN_MEM,
+ 0, NULL, NULL);
+ if (err) {
+ dev_err(&pf->dev, "can't allocat...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [3/4]
...ci_read_base(pf, pci_bar_unknown, res, reg);
+ if (!res->flags)
+ continue;
+
+ size = resource_size(res) * pf->iov->nr_virtfn;
+ res->end = res->start + size - 1;
+ err = pci_bus_alloc_resource(pf->bus, res, size, pf->iov->align,
+ PCIBIOS_MIN_MEM,
+ IORESOURCE_PREFETCH, NULL, NULL);
+ if (err < 0 && (res->flags & IORESOURCE_PREFETCH))
+ err = pci_bus_alloc_resource(pf->bus, res, size,
+ pf->iov->align,
+ PCIBIOS_MIN_MEM,
+ 0, NULL, NULL);
+ if (err) {
+ dev_err(&pf->dev, "can't allocat...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [1/4]
...->resource[pos];
reg = PCI_BASE_ADDRESS_0 + (pos << 2);
- pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -316,7 +317,7 @@ static void pci_read_bases(struct pci_de
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_mem32, res, rom);
}
}
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 1a5fc83..059de16 100644
--- a/drivers/pci/se...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [1/4]
...->resource[pos];
reg = PCI_BASE_ADDRESS_0 + (pos << 2);
- pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -316,7 +317,7 @@ static void pci_read_bases(struct pci_de
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_mem32, res, rom);
}
}
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 1a5fc83..059de16 100644
--- a/drivers/pci/se...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [1/4]
...->resource[pos];
reg = PCI_BASE_ADDRESS_0 + (pos << 2);
- pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -316,7 +317,7 @@ static void pci_read_bases(struct pci_de
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_mem32, res, rom);
}
}
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 1a5fc83..059de16 100644
--- a/drivers/pci/se...
2009 May 20
0
[PATCHv2-RFC 2/2] qemu-kvm: use common code for assigned msix
...ions,
/* handle memory io regions */
if (cur_region->type & IORESOURCE_MEM) {
+ uint32_t size = i == msix_bar_nr(&pci_dev->dev)
+ ? msix_bar_size(&pci_dev->dev) : cur_region->size;
+
int t = cur_region->type & IORESOURCE_PREFETCH
? PCI_ADDRESS_SPACE_MEM_PREFETCH
: PCI_ADDRESS_SPACE_MEM;
/* map physical memory */
+ /* MSI-X table is located outside cur_region->size
+ * and so won't be mapped */
pci_dev->v_addrs[i].e_physbase = cur_...
2009 May 20
0
[PATCHv2-RFC 2/2] qemu-kvm: use common code for assigned msix
...ions,
/* handle memory io regions */
if (cur_region->type & IORESOURCE_MEM) {
+ uint32_t size = i == msix_bar_nr(&pci_dev->dev)
+ ? msix_bar_size(&pci_dev->dev) : cur_region->size;
+
int t = cur_region->type & IORESOURCE_PREFETCH
? PCI_ADDRESS_SPACE_MEM_PREFETCH
: PCI_ADDRESS_SPACE_MEM;
/* map physical memory */
+ /* MSI-X table is located outside cur_region->size
+ * and so won't be mapped */
pci_dev->v_addrs[i].e_physbase = cur_...
2009 May 11
0
[PATCH 2/2] qemu-kvm: use common code for assigned msix
...on *io_regions,
/* handle memory io regions */
if (cur_region->type & IORESOURCE_MEM) {
+ uint32_t size = i == msix_bar_nr(&pci_dev->dev)
+ ? pci_dev->msix_bar_size : cur_region->size;
+
int t = cur_region->type & IORESOURCE_PREFETCH
? PCI_ADDRESS_SPACE_MEM_PREFETCH
: PCI_ADDRESS_SPACE_MEM;
/* map physical memory */
+ /* MSI-X table is located outside cur_region->size
+ * and so won't be mapped */
pci_dev->v_addrs[i].e_physbase = cur_...
2009 May 11
0
[PATCH 2/2] qemu-kvm: use common code for assigned msix
...on *io_regions,
/* handle memory io regions */
if (cur_region->type & IORESOURCE_MEM) {
+ uint32_t size = i == msix_bar_nr(&pci_dev->dev)
+ ? pci_dev->msix_bar_size : cur_region->size;
+
int t = cur_region->type & IORESOURCE_PREFETCH
? PCI_ADDRESS_SPACE_MEM_PREFETCH
: PCI_ADDRESS_SPACE_MEM;
/* map physical memory */
+ /* MSI-X table is located outside cur_region->size
+ * and so won't be mapped */
pci_dev->v_addrs[i].e_physbase = cur_...
2008 Sep 01
1
[PATCH 1/4 v2] PCI: introduce new base functions
...ADDRESS_0 + (pos << 2);
- pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -338,7 +337,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_rom, res, rom);
}
}
@@ -462,12 +461,10 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
if (!child)
return NU...
2008 Sep 01
1
[PATCH 1/4 v2] PCI: introduce new base functions
...ADDRESS_0 + (pos << 2);
- pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -338,7 +337,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_rom, res, rom);
}
}
@@ -462,12 +461,10 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
if (!child)
return NU...
2008 Sep 01
1
[PATCH 1/4 v2] PCI: introduce new base functions
...ADDRESS_0 + (pos << 2);
- pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+ pos += pci_read_base(dev, pci_bar_unknown, res, reg);
}
if (rom) {
@@ -338,7 +337,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
IORESOURCE_SIZEALIGN;
- __pci_read_base(dev, pci_bar_mem32, res, rom);
+ pci_read_base(dev, pci_bar_rom, res, rom);
}
}
@@ -462,12 +461,10 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
if (!child)
return NU...