search for: ioread32_n

..._size); + if (map == NULL) { + nvdev_error(device, "unable to map PRI\n"); + ret = -ENOMEM; goto done; + } + } + /* identify the chipset, and determine classes of subdev/engines */ + if (detect) { /* switch mmio to cpu's native endianness */ #ifndef __BIG_ENDIAN if (ioread32_native(map + 0x000004) != 0x00000000) { @@ -2980,7 +2985,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, /* read boot0 and strapping information */ boot0 = ioread32_native(map + 0x000000); strap = ioread32_native(map + 0x101000); - iounmap(map); /* chipset can be overridden...

...drm/nouveau/core/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c @@ -122,14 +122,14 @@ u32 _nouveau_fifo_channel_rd32(struct nouveau_object *object, u32 addr) { struct nouveau_fifo_chan *chan = (void *)object; - return ((volatile u32 *)chan->user)[addr / 4]; + return ioread32_native(chan->user + addr); } void _nouveau_fifo_channel_wr32(struct nouveau_object *object, u32 addr, u32 data) { struct nouveau_fifo_chan *chan = (void *)object; - ((volatile u32 *)chan->user)[addr / 4] = data; + iowrite32_native(data, chan->user + addr); } static int -- 1.7.8....

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 8ebbe1656..17676c75a 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 8ebbe1656..17676c75a 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++

...uveau/nvkm/subdev/secboot/gm20b.c @@ -142,7 +142,7 @@ gm20b_tegra_read_wpr(struct gm200_secboot *gsb) mc = ioremap(TEGRA_MC_BASE, 0xd00); if (!mc) { nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); - return PTR_ERR(mc); + return -ENOMEM; } gsb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); -- 2.7.4

...ngine/device/base.c index 37589f365..c732074bf 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2924,6 +2924,20 @@ nvkm_device_del(struct nvkm_device **pdevice) } } +static inline bool +nvkm_device_endianness(void __iomem *pri) +{ + u32 boot1 = ioread32_native(pri + 0x000004) & 0x01000001; +#ifdef __BIG_ENDIAN + if (!boot1) + return false; +#else + if (boot1) + return false; +#endif + return true; +} + int nvkm_device_ctor(const struct nvkm_device_func *func, const struct nvkm_device_quirk *quirk, @@ -2973,13 +2987,15 @@ nvkm_device_ctor...

...@ struct nouveau_channel { struct drm_local_map *map; /* mapping of the regs controling the fifo */ - struct drm_local_map *user; + void __iomem *user; uint32_t user_get; uint32_t user_put; @@ -1047,11 +1047,8 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *, #endif /* !ioread32_native */ /* channel control reg access */ -#define nvchan_wr32(reg, val) \ - iowrite32_native((val), \ - (void __force __iomem *)chan->user->handle + (reg)) -#define nvchan_rd32(reg) \ - ioread32_native((void __force __iomem *)chan->user->handle + (reg)) +#define nvchan_wr32(reg, va...

...u64 base, limit; > + u32 value; > > - mc = ioremap(mc_base, 0xd00); > - if (!mc) { > - nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); > - return -ENOMEM; > - } > - sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | > - ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); > - sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) > - << 17; > - cfg = ioread32_native(mc + MC_SECU...

...base.subdev.device; struct nvkm_secboot *sb = &gsb->base; - void __iomem *mc; - u32 cfg; + u64 base, limit; + u32 value; - mc = ioremap(mc_base, 0xd00); - if (!mc) { - nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); - return -ENOMEM; - } - sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | - ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); - sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) - << 17; - cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0); - iounmap(mc); + /* set WPR i...

...r. 3.x but on all kernels we have same error. And try to test several nvidia card GT520, GT610 and other. I tryed to solve the problem by myself and added some debug codes: 1. I added the following debug codes into the file base.c /* read boot0 and strapping information */ boot0 = ioread32_native(map + 0x000000); strap = ioread32_native(map + 0x101000); iounmap(map); printk ("##boot0=%x\n",boot0); printk ("##strap=%x\n",strap); The result you can see in the log_gt610 attachment file. The value of the variable "boot0" for...

...u32 value; > > > > - mc = ioremap(mc_base, 0xd00); > > - if (!mc) { > > - nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); > > - return -ENOMEM; > > - } > > - sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | > > - ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); > > - sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) > > - << 17; > > - cfg = ioread32...

...ubdev/secboot/gm20b.c @@ -48,7 +48,7 @@ gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base) mc = ioremap(mc_base, 0xd00); if (!mc) { nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); - return PTR_ERR(mc); + return -ENOMEM; } sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);

...b.h> +struct evo_object { + struct nouveau_object parent; + void __iomem *iomem; +}; + static u32 nv50_evo_rd32(struct nouveau_object *object, u32 addr) { - void __iomem *iomem = object->oclass->ofuncs->rd08; + void __iomem *iomem = ((struct evo_object *)object)->iomem; return ioread32_native(iomem + addr); } static void nv50_evo_wr32(struct nouveau_object *object, u32 addr, u32 data) { - void __iomem *iomem = object->oclass->ofuncs->rd08; + void __iomem *iomem = ((struct evo_object *)object)->iomem; iowrite32_native(data, iomem + addr); } @@ -60,7 +65,7 @@ n...

...- a/drivers/gpu/drm/nouveau/core/os.h +++ b/drivers/gpu/drm/nouveau/core/os.h @@ -23,17 +23,6 @@ #include <asm/unaligned.h> -static inline int -ffsll(u64 mask) -{ - int i; - for (i = 0; i < 64; i++) { - if (mask & (1ULL << i)) - return i + 1; - } - return 0; -} - #ifndef ioread32_native #ifdef __BIG_ENDIAN #define ioread16_native ioread16be diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 900fae0..b701117 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -270,8 +270,8 @@...

...diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h > index d0ced94ca54c..274b4460bb03 100644 > --- a/drivers/gpu/drm/nouveau/core/os.h > +++ b/drivers/gpu/drm/nouveau/core/os.h > @@ -38,4 +38,21 @@ > #endif /* def __BIG_ENDIAN else */ > #endif /* !ioread32_native */ > > +#if defined(__arm__) > + > +#define nv_cpu_cache_flush_area(va, size) \ > +do { \ > + phys_addr_t pa = virt_to_phys(va); \ > + __cpuc_flush_dcache_area(va, size); \ > + outer_flush_range(pa, pa + size); \ > +} while (0) Couldn't this be a static i...

...rs/gpu/drm/nouveau/core/os.h >> > index d0ced94ca54c..274b4460bb03 100644 >> > --- a/drivers/gpu/drm/nouveau/core/os.h >> > +++ b/drivers/gpu/drm/nouveau/core/os.h >> > @@ -38,4 +38,21 @@ >> > #endif /* def __BIG_ENDIAN else */ >> > #endif /* !ioread32_native */ >> > >> > +#if defined(__arm__) >> > + >> > +#define nv_cpu_cache_flush_area(va, size) \ >> > +do { \ >> > + phys_addr_t pa = virt_to_phys(va); \ >> > + __cpuc_flush_dcache...

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

...nsertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h index d0ced94ca54c..274b4460bb03 100644 --- a/drivers/gpu/drm/nouveau/core/os.h +++ b/drivers/gpu/drm/nouveau/core/os.h @@ -38,4 +38,21 @@ #endif /* def __BIG_ENDIAN else */ #endif /* !ioread32_native */ +#if defined(__arm__) + +#define nv_cpu_cache_flush_area(va, size) \ +do { \ + phys_addr_t pa = virt_to_phys(va); \ + __cpuc_flush_dcache_area(va, size); \ + outer_flush_range(pa, pa + size); \ +} while (0) + +#else + +#define nv_cpu_cache_flush_area(va, size) \ +do { \ +} while...

...reg,mask,val) nouveau_wait_until(dev, 2000000000ULL, (reg), \ (mask), (val)) -/* - * VRAM access for the first 64kB - * see nouveau_state.c - */ -static inline u32 nv_rf32(struct drm_device *dev, unsigned offset) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - return ioread32_native(dev_priv->fb + offset); -} - -static inline void nv_wf32(struct drm_device *dev, unsigned offset, u32 val) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - iowrite32_native(val, dev_priv->fb + offset); -} - /* PRAMIN access */ static inline u32 nv_ri32(struct drm_devi...

...ouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h > > index d0ced94ca54c..274b4460bb03 100644 > > --- a/drivers/gpu/drm/nouveau/core/os.h > > +++ b/drivers/gpu/drm/nouveau/core/os.h > > @@ -38,4 +38,21 @@ > > #endif /* def __BIG_ENDIAN else */ > > #endif /* !ioread32_native */ > > > > +#if defined(__arm__) > > + > > +#define nv_cpu_cache_flush_area(va, size) \ > > +do { \ > > + phys_addr_t pa = virt_to_phys(va); \ > > + __cpuc_flush_dcache_area(va, size); \ > > + outer_flush_range(pa, pa + size); \ > >...