search for: iommus

...u device. This is discovered > by the virtio driver at probe time, but the DMA topology isn't > discoverable and must be described by firmware. For DT the standard IOMMU > description is used, as specified in bindings/iommu/iommu.txt and > bindings/pci/pci-iommu.txt. Like many other IOMMUs, virtio-iommu > distinguishes masters by their endpoint IDs, which requires one IOMMU cell > in the "iommus" property. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com> > --- > Documentation/devicetree/bindings/virtio/mmio.txt | 8 ++++++...

...u device. This is discovered > by the virtio driver at probe time, but the DMA topology isn't > discoverable and must be described by firmware. For DT the standard IOMMU > description is used, as specified in bindings/iommu/iommu.txt and > bindings/pci/pci-iommu.txt. Like many other IOMMUs, virtio-iommu > distinguishes masters by their endpoint IDs, which requires one IOMMU cell > in the "iommus" property. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com> > --- > Documentation/devicetree/bindings/virtio/mmio.txt | 8 ++++++...

...t;> by the virtio driver at probe time, but the DMA topology isn't > >> discoverable and must be described by firmware. For DT the standard IOMMU > >> description is used, as specified in bindings/iommu/iommu.txt and > >> bindings/pci/pci-iommu.txt. Like many other IOMMUs, virtio-iommu > >> distinguishes masters by their endpoint IDs, which requires one IOMMU cell > >> in the "iommus" property. > >> > >> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com> > >> --- > >> Documen...

...wever the DMA relation between devices must be described statically. When a virtio-mmio node is a virtio-iommu device, it needs an "#iommu-cells" property as specified by bindings/iommu/iommu.txt. Otherwise, the virtio-mmio device may perform DMA through an IOMMU, which requires an "iommus" property. Describe these requirements in the device-tree bindings documentation. Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com> --- .../devicetree/bindings/virtio/mmio.txt | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documenta...

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On Tue, 2014-09-02 at 16:42 -0700, Andy Lutomirski wrote: > But there aren't any ACPI systems with both virtio-pci and IOMMUs, > right? So we could say that, henceforth, ACPI systems must declare > whether virtio-pci devices live behind IOMMUs without breaking > backward compatibility. I don't know for sure whether that's the case and whether we can rely on that not happening, we'll need x86 folks o...

On Tue, 2014-09-02 at 16:42 -0700, Andy Lutomirski wrote: > But there aren't any ACPI systems with both virtio-pci and IOMMUs, > right? So we could say that, henceforth, ACPI systems must declare > whether virtio-pci devices live behind IOMMUs without breaking > backward compatibility. I don't know for sure whether that's the case and whether we can rely on that not happening, we'll need x86 folks o...

...t;> to expose a physically-addressed virtio-pci device to the guest behind >> an emulated IOMMU. QEMU may already be doing that on ppc64, but it >> isn't on x86_64 or arm (yet). > > Last I looked, it does on everything, it bypasses the DMA layer in qemu > which is where IOMMUs are implemented. I believe you, but I'm not convinced that this means much from the guest's POV, except on ppc64. > >> On x86_64, I'm pretty sure that QEMU can emulate an IOMMU for >> everything except the virtio-pci devices. The ACPI DMAR stuff is >> quite expre...

...s discovered >> by the virtio driver at probe time, but the DMA topology isn't >> discoverable and must be described by firmware. For DT the standard IOMMU >> description is used, as specified in bindings/iommu/iommu.txt and >> bindings/pci/pci-iommu.txt. Like many other IOMMUs, virtio-iommu >> distinguishes masters by their endpoint IDs, which requires one IOMMU cell >> in the "iommus" property. >> >> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com> >> --- >> Documentation/devicetree/bindings/vir...

On Tue, Sep 2, 2014 at 3:10 PM, Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote: > On Tue, 2014-09-02 at 14:37 -0700, Andy Lutomirski wrote: > >> Let's take a step back from from the implementation. What is a driver >> for a virtio PCI device (i.e. a PCI device with vendor 0x1af4) >> supposed to do on ppc64? > > Today, it's supposed to send

On Tue, Sep 2, 2014 at 3:10 PM, Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote: > On Tue, 2014-09-02 at 14:37 -0700, Andy Lutomirski wrote: > >> Let's take a step back from from the implementation. What is a driver >> for a virtio PCI device (i.e. a PCI device with vendor 0x1af4) >> supposed to do on ppc64? > > Today, it's supposed to send

...traight-up bug for QEMU > to expose a physically-addressed virtio-pci device to the guest behind > an emulated IOMMU. QEMU may already be doing that on ppc64, but it > isn't on x86_64 or arm (yet). Last I looked, it does on everything, it bypasses the DMA layer in qemu which is where IOMMUs are implemented. > On x86_64, I'm pretty sure that QEMU can emulate an IOMMU for > everything except the virtio-pci devices. The ACPI DMAR stuff is > quite expressive. Well, *except* virtio, exactly... > On ARM, I hope the QEMU will never implement a PCI IOMMU. As far as I >...

...traight-up bug for QEMU > to expose a physically-addressed virtio-pci device to the guest behind > an emulated IOMMU. QEMU may already be doing that on ppc64, but it > isn't on x86_64 or arm (yet). Last I looked, it does on everything, it bypasses the DMA layer in qemu which is where IOMMUs are implemented. > On x86_64, I'm pretty sure that QEMU can emulate an IOMMU for > everything except the virtio-pci devices. The ACPI DMAR stuff is > quite expressive. Well, *except* virtio, exactly... > On ARM, I hope the QEMU will never implement a PCI IOMMU. As far as I >...

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Xen Security Advisory CVE-2013-0153 / XSA-36 version 3 interrupt remap entries shared and old ones not cleared on AMD IOMMUs UPDATES IN VERSION 3 ==================== Public release. ISSUE DESCRIPTION ================= To avoid an erratum in early hardware, the Xen AMD IOMMU code by default chooses to use a single interrupt remapping table for the whole system. This sharing implies that any guest with a passed throu...

...iommu device. > > The virtio-pci-iommu is conceptually split between a PCI programming > interface and a translation component on the parent bus. The latter > doesn't have a node in the device tree. The virtio-pci-iommu node > describes both, by linking the PCI endpoint to "iommus" property of DMA > master nodes and to "iommu-map" properties of bus nodes. > > Reviewed-by: Rob Herring <robh at kernel.org> > Reviewed-by: Eric Auger <eric.auger at redhat.com> > Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com&g...

...n for Device Assignment Structure. It means using default policy. On the other hand, Address Translation Structure exists per guest domain. So, it needs allocating the memory for Address Translation Structure from NUMA node which guest domain runs. This patch is useful for a system which has many IOMMUs. Thanks, -- Yuji Shimada Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp> diff -r 5fd51e1e9c79 xen/drivers/passthrough/vtd/intremap.c --- a/xen/drivers/passthrough/vtd/intremap.c Wed Nov 05 10:57:21 2008 +0000 +++ b/xen/drivers/passthrough/vtd/intremap.c Tue Nov 18 17:37:31 2008...

...st, I doubt that we'll ever see a physically addressed > > PCI virtio device for which ACPI advertises an IOMMU, since any sane > > hypervisor will just not advertise an IOMMU for the virtio device. > > But are there arm64 or PPC guests that use virtio_pci, that have > > IOMMUs, and that will malfunction if the virtio_pci driver ends up > > using the IOMMU? I certainly hope not, since these systems might be > > very hard-pressed to work right if someone plugged in a physical > > virtio-speaking PCI device. > > It will definitely not work on ppc64...

...st, I doubt that we'll ever see a physically addressed > > PCI virtio device for which ACPI advertises an IOMMU, since any sane > > hypervisor will just not advertise an IOMMU for the virtio device. > > But are there arm64 or PPC guests that use virtio_pci, that have > > IOMMUs, and that will malfunction if the virtio_pci driver ends up > > using the IOMMU? I certainly hope not, since these systems might be > > very hard-pressed to work right if someone plugged in a physical > > virtio-speaking PCI device. > > It will definitely not work on ppc64...

Hello everyone, Reposting with after having applied the (minor) fixes suggested by Wei and Jan. Allen, if you can tell us what you think about this, or suggest someone else to ask some feedback to, if you''re no longer involved with VT-d, that would be great! :-) -- As already discussed here [1], dealing with IOMMU faults in interrupt context may cause nasty things to happen, up to

...e to describe the virtio-iommu device. The virtio-pci-iommu is conceptually split between a PCI programming interface and a translation component on the parent bus. The latter doesn't have a node in the device tree. The virtio-pci-iommu node describes both, by linking the PCI endpoint to "iommus" property of DMA master nodes and to "iommu-map" properties of bus nodes. Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker at arm.com> --- .../devicetree/bindings/virtio/iommu.txt | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 D...