Displaying 5 results from an estimated 5 matches for "iommu_hap_pt_shar".
Did you mean:
iommu_hap_pt_share
2011 Mar 25
2
[RFC PATCH 2/3] AMD IOMMU: Implement p2m sharing
--
Advanced Micro Devices GmbH
Sitz: Dornach, Gemeinde Aschheim,
Landkreis München Registergericht München,
HRB Nr. 43632
WEEE-Reg-Nr: DE 12919551
Geschäftsführer:
Alberto Bozzo, Andrew Bowd
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
2011 Jul 30
22
[bug] ''VT-d 1G super page'' feature is blocked
Hi Tim,
Could you please have a look at this bug? Thanks a lot.
http://bugzilla.xensource.com/bugzilla/show_bug.cgi?id=1774
Best Regards,
Yongjie Ren (Jay)
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
2012 Mar 01
14
[PATCH 0 of 3] RFC Paging support for AMD NPT V2
There has been some progress, but still no joy. Definitely not intended for
inclusion at this point.
Tim, Wei, I added a Xen command line toggle to disable IOMMU and P2M table
sharing.
Tim, I verified that changes to p2m-pt.c don''t break shadow mode (64bit
hypervisor and Win 7 guest).
Hongkaixing, I incorporated your suggestion in patch 2, so I should add your
Signed-off-by eventually.
2013 May 02
5
[PATCH] x86: allow Dom0 read-only access to IO-APICs
There are BIOSes that want to map the IO-APIC MMIO region from some
ACPI method(s), and there is at least one BIOS flavor that wants to
use this mapping to clear an RTE''s mask bit. While we can''t allow the
latter, we can permit reads and simply drop write attempts, leveraging
the already existing infrastructure introduced for dealing with AMD
IOMMUs'' representation as
2012 Dec 10
26
[PATCH 00/11] Add virtual EPT support Xen.
From: Zhang Xiantao <xiantao.zhang@intel.com>
With virtual EPT support, L1 hyerpvisor can use EPT hardware
for L2 guest''s memory virtualization. In this way, L2 guest''s
performance can be improved sharply. According to our testing,
some benchmarks can show > 5x performance gain.
Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com>
Zhang Xiantao (11):