search for: iommu_domain_alloc

iommu_domain_alloc returns NULL on error so replace an incorrect IS_ERR check with a NULL check. The Coccinelle semantic patch used to find this issue is as follows: @@ expression e; statement S; @@ *e = iommu_domain_alloc(...); if (IS_ERR(e)) S Signed-off-by: Amitoj Kaur Chawla <amitoj1606 at gmail.com> ---...

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn> In case of error, the function iommu_domain_alloc() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) di...

'iommu_domain_alloc()' returns NULL in case of error, not an error pointer. So test it accordingly. Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm...

...gt; case just doesn't fit into the current API model at all. We need the > > IOMMU driver to somehow know about the specific details of which > > devices have magic associations with specific contexts, and we > > almost certainly need a more expressive interface than > > iommu_domain_alloc() to have any hope of reliable results. > > This is correct for Qualcomm GPUs - The GPU hardware context switching > requires a specific context and there are some restrictions around > secure contexts as well. > > We don't really care if the DMA attaches to a context just a...

...ve a similar thing too, and AFAICS that case just doesn't fit into the current API model at all. We need the IOMMU driver to somehow know about the specific details of which devices have magic associations with specific contexts, and we almost certainly need a more expressive interface than iommu_domain_alloc() to have any hope of reliable results. Robin. > Some of the above is due to a SW driver model (and its work-in-progress > status), other is due to a HW model. So essentially we need a way for a driver > to tell the core not to mess with IOMMU stuff of drivers device behind the > dri...

...#39;t fit into the current API model at all. We need the > > > IOMMU driver to somehow know about the specific details of which > > > devices have magic associations with specific contexts, and we > > > almost certainly need a more expressive interface than > > > iommu_domain_alloc() to have any hope of reliable results. > > > > This is correct for Qualcomm GPUs - The GPU hardware context switching > > requires a specific context and there are some restrictions around > > secure contexts as well. > > > > We don't really care if the DM...

On Wed, Jul 6, 2016 at 9:23 PM, <weiyj_lk at 163.com> wrote: > From: Wei Yongjun <yongjun_wei at trendmicro.com.cn> > > In case of error, the function iommu_domain_alloc() returns NULL > pointer not ERR_PTR(). The IS_ERR() test in the return value check > should be replaced with NULL test. Reviewed-by: Alexandre Courbot <acourbot at nvidia.com> Thanks!

...st Driver unbind */ extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops); +extern int bus_iommu_probe(struct bus_type *bus); extern bool iommu_present(struct bus_type *bus); extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap); extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); -- 2.17.1

...o, and AFAICS that > case just doesn't fit into the current API model at all. We need the > IOMMU driver to somehow know about the specific details of which > devices have magic associations with specific contexts, and we > almost certainly need a more expressive interface than > iommu_domain_alloc() to have any hope of reliable results. This is correct for Qualcomm GPUs - The GPU hardware context switching requires a specific context and there are some restrictions around secure contexts as well. We don't really care if the DMA attaches to a context just as long as it doesn't atta...

From: Thierry Reding <treding at nvidia.com> The nouveau_fence_get_get_driver_name() function has a redundant _get in its name. Remove it. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nouveau_fence.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c

...PI model at all. We need the > >>>> IOMMU driver to somehow know about the specific details of which > >>>> devices have magic associations with specific contexts, and we > >>>> almost certainly need a more expressive interface than > >>>> iommu_domain_alloc() to have any hope of reliable results. > >>> > >>> This is correct for Qualcomm GPUs - The GPU hardware context switching > >>> requires a specific context and there are some restrictions around > >>> secure contexts as well. > >>> >...

...t into the current API model at all. We need the >>>> IOMMU driver to somehow know about the specific details of which >>>> devices have magic associations with specific contexts, and we >>>> almost certainly need a more expressive interface than >>>> iommu_domain_alloc() to have any hope of reliable results. >>> >>> This is correct for Qualcomm GPUs - The GPU hardware context switching >>> requires a specific context and there are some restrictions around >>> secure contexts as well. >>> >>> We don't reall...

On Fri, Jul 27, 2018 at 10:25:13AM +0200, Joerg Roedel wrote: > On Fri, Jul 27, 2018 at 02:16:18AM +0300, Dmitry Osipenko wrote: > > The proposed solution adds a new option to the base device driver > > structure that allows device drivers to explicitly convey to the drivers > > core that the implicit IOMMU backing for devices must not happen. > > Why is IOMMU mapping a

...all. We need the >>>>>> IOMMU driver to somehow know about the specific details of which >>>>>> devices have magic associations with specific contexts, and we >>>>>> almost certainly need a more expressive interface than >>>>>> iommu_domain_alloc() to have any hope of reliable results. >>>>> >>>>> This is correct for Qualcomm GPUs - The GPU hardware context switching >>>>> requires a specific context and there are some restrictions around >>>>> secure contexts as well. >>>...

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

With linux-next-2017-12-14, I get a crash when nouveau is loaded by systemd-udevd. [ 12.050625] Unable to handle kernel NULL pointer dereference at virtual address 00000058 [ 12.050627] Mem abort info: [ 12.050628] ESR = 0x96000004 [ 12.050630] Exception class = DABT (current EL), IL = 32 bits [ 12.050631] SET = 0, FnV = 0 [ 12.050632] EA = 0, S1PTW = 0 [ 12.050633] Data