Displaying 5 results from an estimated 5 matches for "iohl".
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ihl
2007 Jan 10
0
[LLVMdev] Pattern matching questions
...PPC backend, which has the exact same issue
> for integer constants.
Actually, for SPU, not quite the same:
def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val),
"ilhu $rT, $val", LoadNOP,
[(set GPRC:$rT, immZExt16:$val)]>;
def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val),
"iohl $rT, $val", LoadNOP,
[(set GPRC:$rT, immZExt16:$val)]>;
Thus, you can't really do as the PPC does, viz:
(ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))
vs.
(IOHL (ILHU (HI...
2007 Jan 09
2
[LLVMdev] Pattern matching questions
...eal with multiple instruction sequences in a pattern?
>> To load a constant is a two instruction sequence, but both
>> instructions only take two operands (assume that r3 is a 32-bit
>> register):
>>
>> ilhu $3, 45 # r3 = (45 << 16)
>> iohl $3, 5 # r3 |= 5
>>
>> I tried:
>>
>> def : Pat<(i32 imm:$imm),
>> (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>;
>
> It is possible to write multi-instruction pattern, e.g.
> X86InstrSSE.td line 1911. But how are you defini...
2007 Jan 11
1
[LLVMdev] Pattern matching questions
...ssue
>> for integer constants.
>
> Actually, for SPU, not quite the same:
>
> def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val),
> "ilhu $rT, $val", LoadNOP,
> [(set GPRC:$rT, immZExt16:$val)]>;
>
> def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val),
> "iohl $rT, $val", LoadNOP,
> [(set GPRC:$rT, immZExt16:$val)]>;
>
> Thus, you can't really do as the PPC does, viz:
>
> (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm...
2007 Jan 09
3
[LLVMdev] Pattern matching questions
...DK defines.
Three quick questions:
- How does one deal with multiple instruction sequences in a pattern?
To load a constant is a two instruction sequence, but both
instructions only take two operands (assume that r3 is a 32-bit
register):
ilhu $3, 45 # r3 = (45 << 16)
iohl $3, 5 # r3 |= 5
I tried:
def : Pat<(i32 imm:$imm),
(IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>;
- The return instruction for Cell SPU is "bi $lr". How do I jam that
into the instruction info w/o tblgen bitching up a storm about the
"$&quo...
2007 Jan 09
0
[LLVMdev] Pattern matching questions
...t;
> - How does one deal with multiple instruction sequences in a pattern?
> To load a constant is a two instruction sequence, but both
> instructions only take two operands (assume that r3 is a 32-bit
> register):
>
> ilhu $3, 45 # r3 = (45 << 16)
> iohl $3, 5 # r3 |= 5
>
> I tried:
>
> def : Pat<(i32 imm:$imm),
> (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>;
It is possible to write multi-instruction pattern, e.g.
X86InstrSSE.td line 1911. But how are you defining HI16 and LO16?
Sounds like...