search for: ioh3420

Displaying 18 results from an estimated 18 matches for "ioh3420".

2018 Sep 05
1
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...cess to the emulated bridge is already sufficient. The Prefetchable > Base Upper 32 Bits register is at offset 0x28. > > In a trace where the Nvidia device is disabled/enabled via Device > Manager, I see writes on the enable path: > > 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4) Did you do anything special to get an emulated bridge included in this setup? Folllowing the instructions at https://wiki.archlinux.org/index.php/PCI_passthrough_via_OVMF I can successfully pass through devices to windows running under virt-manager. In the nvidia GPU case I...
2018 Apr 26
2
Re: how xml generated
oh, there is much much much code,it's too too too hard for me. So,,,,,can i ask more question:use virt-manager create a domain,but with a result of "unsupported configuration:the ioh3420 controller is not supported in this qemu".since it's arm64 platform,and ioh3420 is a intel device.right?Why produce a intel device in arm64 platform? So, can i delete the ioh3420 only by changing the code?info: i use the libvirt-2.0.0,virt-manager create doamin succeed;when i update to li...
2018 Apr 30
2
Re: connecting host and guest vm using a dummy nic
...get chassisNr='2'/> <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> <model name='ioh3420'/> <target chassis='3' port='0x8'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='...
2018 May 01
0
Re: connecting host and guest vm using a dummy nic
...'/> > <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> > </controller> > <controller type='pci' index='3' model='pcie-root-port'> > <model name='ioh3420'/> > <target chassis='3' port='0x8'/> > <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0' multifunction='on'/> > </controller> > <controller type='...
2018 Apr 26
0
Re: how xml generated
On 04/26/2018 10:46 AM, lizhuoyao wrote: > oh, there is much much much code,it's too too too hard for me. > > So,,,,,can i ask more question:use virt-manager create a domain,but with a result of "unsupported configuration:the ioh3420 controller is not supported in this qemu".since it's arm64 platform,and ioh3420 is a intel device.right?Why produce a intel device in arm64 platform? I don't think there's a way to step into virt-manager's process of defining domains. However, you can use virt-install directly...
2018 Apr 27
2
connecting host and guest vm using a dummy nic
Greetings all, I have a host machine that runs a router within a vm. I want to allow a connection between the host and the guest so the host can connect to the lan provided by the router vm. I've created a dummy interface with these commands: $ ip link add ens99-dummy type dummy $ ip link set ens99-dummy address 52:54:00:1f:d0:ff this resulted with this output: $ ifconfig ens99-dummy
2018 Apr 26
2
Re: how xml generated
Thanks for your reply what i want to know is that why there are many devices in $domain.xml, actully , i choose nothing in virt-manager? so, Do i need to look at qemuDomainDefineXMLFlags()? hours ago, i thought it's qemuDomainCreateWithFlags. -- Have a good day > -----原始邮件----- > 发件人: Michal Privoznik <mprivozn@redhat.com> > 发送时间: 2018年4月26日 星期四 > 收件人: "李卓瑶"
2018 May 01
2
Re: connecting host and guest vm using a dummy nic
...<address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> > > </controller> > > <controller type='pci' index='3' model='pcie-root-port'> > > <model name='ioh3420'/> > > <target chassis='3' port='0x8'/> > > <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0' multifunction='on'/> > > </controller> > > <c...
2018 Aug 30
2
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...cess to the emulated bridge is already sufficient. The Prefetchable > Base Upper 32 Bits register is at offset 0x28. > > In a trace where the Nvidia device is disabled/enabled via Device > Manager, I see writes on the enable path: > > 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4) > > For Linux, I only see one write at startup, none on runtime resume. > I did not test system sleep/resume. (disable/enable is arguably a bit > different from system s/r, you may want to do additional testing here.) I managed to install Win10 Home under virt-man...
2015 Aug 12
2
PCI passthrough fails in virsh: iommu group is not viable
...d some USB controllers passed-through. I am able to run one of the guests like this (assuming vfio stuff has happened elsewhere), but I would prefer to use virsh: kvm -M q35 -m 8192 -cpu host,kvm=off \ -smp 4,sockets=1,cores=4,threads=1 \ -bios /usr/share/seabios/bios.bin -vga none \ -device ioh3420,bus=pcie.0,addr=1c.0,multifunction=on,port=1,chassis=1,id=root.1 \ -device vfio-pci,host=02:00.0,bus=root.1,addr=00.0,multifunction=on,x-vga=on \ -device vfio-pci,host=02:00.1,bus=root.1,addr=00.1 \ -device vfio-pci,host=00:1d.0,bus=pcie.0 \ -device vfio-pci,host=00:1a.0,bus=pcie.0 \ -nog...
2018 Aug 30
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...already sufficient. The Prefetchable > > Base Upper 32 Bits register is at offset 0x28. > > > > In a trace where the Nvidia device is disabled/enabled via Device > > Manager, I see writes on the enable path: > > > > 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4) > > > > For Linux, I only see one write at startup, none on runtime resume. > > I did not test system sleep/resume. (disable/enable is arguably a bit > > different from system s/r, you may want to do additional testing here.) > > I managed to ins...
2015 Aug 12
0
Re: PCI passthrough fails in virsh: iommu group is not viable
...ugh. I am able to run one of the guests like > this (assuming vfio stuff has happened elsewhere), but I would prefer to use > virsh: > > kvm -M q35 -m 8192 -cpu host,kvm=off \ > -smp 4,sockets=1,cores=4,threads=1 \ > -bios /usr/share/seabios/bios.bin -vga none \ > -device ioh3420,bus=pcie.0,addr=1c.0,multifunction=on,port=1,chassis=1,id=root.1 \ > -device vfio-pci,host=02:00.0,bus=root.1,addr=00.0,multifunction=on,x-vga=on \ > -device vfio-pci,host=02:00.1,bus=root.1,addr=00.1 \ > -device vfio-pci,host=00:1d.0,bus=pcie.0 \ > -device vfio-pci,host=00:1a.0...
2015 Sep 24
1
Re: PCI passthrough fails in virsh: iommu group is not viable
...y pass the GPU through so the guest OS detects it and is able to make use of the attached display? Thanks, Alex > > > > kvm -M q35 -m 8192 -cpu host,kvm=off \ > > -smp 4,sockets=1,cores=4,threads=1 \ > > -bios /usr/share/seabios/bios.bin -vga none \ > > -device ioh3420,bus=pcie.0,addr=1c.0,multifunction=on,port=1,chassis=1,id=root.1 \ > > -device vfio-pci,host=02:00.0,bus=root.1,addr=00.0,multifunction=on,x-vga=on \ > > -device vfio-pci,host=02:00.1,bus=root.1,addr=00.1 \ > > -device vfio-pci,host=00:1d.0,bus=pcie.0 \ > > -device v...
2016 Jun 28
1
Use USB2.0 Camera with KVM based VM
Hey All, I've been googleing this issue for hours but I can't find a workable solution. I found a reply to a bug posting that said the USB hub on the VM defaults to USB 1.1. I see this is true when I lsusb on the CentOS 7 guest. The reply to the bug post went on to say that the problem is that the USB 2.0 camera will not work with the USB 1.1 default hub and that I should change the
2018 Aug 28
6
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
On Fri, Aug 24, 2018 at 11:42 PM, Peter Wu <peter at lekensteyn.nl> wrote: > Are these systems also affected through runtime power management? For > example: > > modprobe nouveau # should enable runtime PM > sleep 6 # wait for runtime suspend to kick in > lspci -s1: # runtime resume by reading PCI config space > > On laptops from
2018 Aug 28
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...uest, but perhaps logging access to the emulated bridge is already sufficient. The Prefetchable Base Upper 32 Bits register is at offset 0x28. In a trace where the Nvidia device is disabled/enabled via Device Manager, I see writes on the enable path: 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4) For Linux, I only see one write at startup, none on runtime resume. I did not test system sleep/resume. (disable/enable is arguably a bit different from system s/r, you may want to do additional testing here.) Full log for WIndows 10 and Linux: https://github.com/Lekensteyn/...
2012 Jan 24
2
[PATCH 26/28] pci: convert to QEMU Object Model
...| 23 ++++-- hw/i82378.c | 31 ++++--- hw/ide/cmd646.c | 36 +++++--- hw/ide/ich.c | 31 ++++--- hw/ide/piix.c | 79 +++++++++++------- hw/ide/via.c | 27 ++++-- hw/intel-hda.c | 56 ++++++++---- hw/ioh3420.c | 59 +++++++------ hw/ivshmem.c | 47 ++++++---- hw/lsi53c895a.c | 31 ++++--- hw/macio.c | 19 +++-- hw/ne2000.c | 35 +++++--- hw/pci.c | 123 ++++++++++++--------------- hw/pci.h...
2018 Aug 31
6
[PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
On over 40 Intel-based Asus products, the nvidia GPU becomes unusable after S3 suspend/resume. The affected products include multiple generations of nvidia GPUs and Intel SoCs. After resume, nouveau logs many errors such as: fifo: fault 00 [READ] at 0000005555555000 engine 00 [GR] client 04 [HUB/FE] reason 4a [] on channel -1 [007fa91000 unknown] DRM: failed to idle channel 0 [DRM]