Displaying 2 results from an estimated 2 matches for "ioapicst".
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ioapics
2009 May 20
9
[PATCH] qemu: msi irq allocation api
...SI_DATA_VECTOR_SHIFT 0
+#define MSI_DATA_VECTOR_MASK 0x000000ff
+#define MSI_DATA_DELIVERY_MODE_SHIFT 8
+#define MSI_ADDR_DEST_MODE_SHIFT 2
+#define MSI_DATA_TRIGGER_SHIFT 15
+#define MSI_ADDR_DEST_ID_SHIFT 12
+#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
+#define MSI_DATA_LEVEL_SHIFT 14
+
struct IOAPICState {
uint8_t id;
uint8_t ioregsel;
@@ -51,6 +62,11 @@ struct IOAPICState {
uint64_t ioredtbl[IOAPIC_NUM_PINS];
};
+struct msi_state {
+ uint64_t addr;
+ uint32_t data;
+};
+
static void ioapic_service(IOAPICState *s)
{
uint8_t i;
@@ -259,3 +275,52 @@ IOAPICState *ioap...
2009 May 20
9
[PATCH] qemu: msi irq allocation api
...SI_DATA_VECTOR_SHIFT 0
+#define MSI_DATA_VECTOR_MASK 0x000000ff
+#define MSI_DATA_DELIVERY_MODE_SHIFT 8
+#define MSI_ADDR_DEST_MODE_SHIFT 2
+#define MSI_DATA_TRIGGER_SHIFT 15
+#define MSI_ADDR_DEST_ID_SHIFT 12
+#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
+#define MSI_DATA_LEVEL_SHIFT 14
+
struct IOAPICState {
uint8_t id;
uint8_t ioregsel;
@@ -51,6 +62,11 @@ struct IOAPICState {
uint64_t ioredtbl[IOAPIC_NUM_PINS];
};
+struct msi_state {
+ uint64_t addr;
+ uint32_t data;
+};
+
static void ioapic_service(IOAPICState *s)
{
uint8_t i;
@@ -259,3 +275,52 @@ IOAPICState *ioap...