search for: ioapic_write_entry

...ad_entry(int apic, int pin, int raw) +{ + struct IO_APIC_route_entry entry; + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + entry = __ioapic_read_entry(apic, pin, raw); + spin_unlock_irqrestore(&ioapic_lock, flags); + return entry; +} + +static void +__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + void (*write)(unsigned int, unsigned int, unsigned int) + = raw ? __io_apic_write : io_apic_write; + union entry_union eu = {{0, 0}}; + + eu.entry = e; + (*write)(apic, 0x11 + 2*pin, eu.w2); + (*write)(apic, 0x10 +...

...ad_entry(int apic, int pin, int raw) +{ + struct IO_APIC_route_entry entry; + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + entry = __ioapic_read_entry(apic, pin, raw); + spin_unlock_irqrestore(&ioapic_lock, flags); + return entry; +} + +static void +__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + void (*write)(unsigned int, unsigned int, unsigned int) + = raw ? __io_apic_write : io_apic_write; + union entry_union eu = {{0, 0}}; + + eu.entry = e; + (*write)(apic, 0x11 + 2*pin, eu.w2); + (*write)(apic, 0x10 +...

...etect processors subject to AMD erratum #121 and refuse to boot." since xen 4.1.3 and results in the following stacktrace: find_iommu_for_device amd_iommu_ioapic_update_ire timer_interrupt enable_8259_A_irq do_IRQ printk_start_of_line acpi_os_printf io_apic_write __ioapic_write_entry ioapic_write_entry __clear_IO_APIC_pin clear_IO_APIC disable_IO_APIC __stop_this_cpu smp_send_stop machine_restart panic tasklet_schedule_on_cpu display_cacheinfo init_amd generic_identify identify_cpu _start_xen _high_start This patch fixes this by ke...

...boot." Instead of the actual panic-message from the patch the following stacktrace appears (i typed it down from screen, so it might contain typos) find_iommu_for_device amd_iommu_ioapic_update_ire timer_interrupt enable_8259_A_irq do_IRQ printk_start_of_line acpi_os_printf io_apic_write __ioapic_write_entry ioapic_write_entry __clear_IO_APIC_pin clear_IO_APIC disable_IO_APIC __stop_this_cpu smp_send_stop machine_restart panic tasklet_schedule_on_cpu display_cacheinfo init_amd generic_identify identify_cpu _start_xen _high_start Panic on CPU 0: Xen BUG at pci_amd_iommu.c:33 ===== The patch in the ne...

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine